outrststat

         Contains Output Clock Counter Reset acknowledge status.
      
Module Instance Base Address Register Address
i_clk_mgr_mainpllgrp 0xFFD04040 0xFFD040A4

Offset: 0x64

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

outresetack

RO 0x0

outrststat Fields

Bit Name Description Access Reset
15:0 outresetack
These read only bits per PLL output indicate that the PLL has received the Output Reset Counter request and has gracefully stopped the respective PLL output clock.
For software to change the PLL output counter without producing glitches on the respective clock, SW must set the Output Counter Reset Register 'Output Counter Reset' bit. Software then polls the respective Output Counter Reset Acknowledge bit in the Output Counter Reset Ack Status Register. Software then writes the appropriate counter register, and then clears the respective Output Counter Reset bit.

The reset value of this bit is applied on a cold reset; warm reset has no affect on this bit.
Value Description
0 IDLE
1 ACK_RECEIVED
RO 0x0