cntr3clk

         Contains settings that control Counter 3 clock generated from the Main PLL VCO clock.
      
Module Instance Base Address Register Address
i_clk_mgr_mainpllgrp 0xFFD04040 0xFFD0406C

Offset: 0x2C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cnt

RW 0x0

cntr3clk Fields

Bit Name Description Access Reset
10:0 cnt
Divides the VCO frequency by the value+1 in this field.
RW 0x0