bypass

         Contains fields that control bypass for clocks derived from the Main PLL.
1: The clock is bypassed to boot_clk.
0: The clock is derived from the 5:1 active mux.
      
Module Instance Base Address Register Address
i_clk_mgr_mainpllgrp 0xFFD04040 0xFFD04054

Offset: 0x14

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

fben

RW 0x1

rfen

RW 0x1

hmcpllref

RW 0x1

s2fuser0

RW 0x1

noc

RW 0x1

mpu

RW 0x1

bypass Fields

Bit Name Description Access Reset
5 fben
If set, the pll_main_fben_clk will be bypassed to the boot_clk.  The pll_main_fben_clk is used to synchronously update the Numerator to the Main PLL.
RW 0x1
4 rfen
If set, the pll_main_rfen_clk will be bypassed to the boot_clk.  The pll_main_rfen_clk is used to synchronously update the Denominator to the Main PLL.
RW 0x1
3 hmcpllref
If set, the hmc_pll_ref_clk will be bypassed to the boot_clk.
RW 0x1
2 s2fuser0
If set, the s2f_user0_clk will be bypassed to the boot_clk.
RW 0x1
1 noc
If set, the NOC clock group will be bypassed to boot_clk.
RW 0x1
0 mpu
If set, the MPU clock group will be bypassed to the boot_clk.
RW 0x1