testioctrl

         Contains fields setting the IO output select for Test Clock and Debug outputs.    The dedicated IO outputs includes two outputs for the Main PLL clock outputs (PLL_CLK0 and PLL_CLK1), two outputs for the Peripheral PLL clock outputs (PLL_CLK2 and PLL_CLK3), and one output for miscelaneous debug for the Main and Peripheral PLL (PLL_CLK4).

The Test Clock and Debug outputs will only propagate to the dedicated IO based on the IO pinmux configuration.  If Test Clocks are selected in the pinmux, then the selects in this register determine which PLL clocks and PLL debug signals will propagate to the IOs.

Module Instance	Base Address	Register Address
`i_clk_mgr_clkmgr`	`0xFFD04000`	`0xFFD04020`

Offset: 0x20

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`											`debugclksel` `RW 0x10`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`				`periclksel` `RW 0x8`				`Reserved`				`mainclksel` `RW 0x8`

testioctrl Fields

Bit	Name	Description	Access	Reset
20:16	`debugclksel`	Selects the source of PLL_CLK4 for miscellaneous PLL signals. Bit[3] (p below) determines if from the debug output is from the Main or Peripheral PLL. If 0, the the output is from the Main PLL and if 1, the output is from the Peripheral PLL. The following table determines the PLL debug output select: sel PLL_CLK4 0p000 OUTRESETACK0 0p001 OUTRESETACK3 0p010 OUTRESETACK7 0p011 PLLRESET 0p100 OUTRESETACK15 0p101 FBSLIP 0p110 RFSLIP 0p111 LOCK 1xxxx VSS	`RW`	`0x10`
11:8	`periclksel`	Selects the source of PLL_CLK2 and PLL_CLK3 dedicated IO outputs if selected. All of the CLKOUT# counter outputs are from the Peripheral PLL. The following table determines the PLL counter output select: sel PLL_CLK2 PLL_CLK3 0000 CLKOUT0 CLKOUT8 0001 CLKOUT1 CLKOUT9 0010 CLKOUT2 CLKOUT10 0011 CLKOUT3 CLKOUT11 0100 CLKOUT4 CLKOUT13 0101 CLKOUT5 CLKOUT14 0110 CLKOUT6 CLKOUT15 0111 CLKOUT7 CLKOUT16 1xxx VSS VSS	`RW`	`0x8`
3:0	`mainclksel`	Selects the source of PLL_CLK0 and PLL_CLK1 dedicated IO outputs if selected. All of the CLKOUT# counter outputs are from the Main PLL. The following table determines the PLL counter output select: sel PLL_CLK0 PLL_CLK1 0000 CLKOUT0 CLKOUT8 0001 CLKOUT1 CLKOUT9 0010 CLKOUT2 CLKOUT10 0011 CLKOUT3 CLKOUT11 0100 CLKOUT4 CLKOUT13 0101 CLKOUT5 CLKOUT14 0110 CLKOUT6 CLKOUT15 0111 CLKOUT7 CLKOUT16 1xxx VSS VSS	`RW`	`0x8`

Bit

Name

Description

Access

Reset

20:16

debugclksel

Selects the source of PLL_CLK4 for miscellaneous PLL signals.   

Bit[3]  (p below) determines if from the debug output is from the Main or Peripheral PLL.  If 0, the the output is from the Main PLL and if 1, the output is from the Peripheral PLL.

The following table determines the PLL debug output select:

sel			PLL_CLK4
0p000		OUTRESETACK0
0p001		OUTRESETACK3
0p010		OUTRESETACK7
0p011		PLLRESET
0p100		OUTRESETACK15
0p101		FBSLIP
0p110		RFSLIP
0p111		LOCK
1xxxx		VSS

RW

0x10

11:8

periclksel

Selects the source of PLL_CLK2 and PLL_CLK3 dedicated IO outputs if selected.  All of the CLKOUT# counter outputs are from the Peripheral PLL.

The following table determines the PLL counter output select:

sel			PLL_CLK2		PLL_CLK3
0000		CLKOUT0		CLKOUT8
0001		CLKOUT1		CLKOUT9
0010		CLKOUT2		CLKOUT10
0011		CLKOUT3		CLKOUT11
0100		CLKOUT4		CLKOUT13
0101		CLKOUT5		CLKOUT14
0110		CLKOUT6		CLKOUT15
0111		CLKOUT7		CLKOUT16
1xxx		VSS				VSS

RW

0x8

3:0

mainclksel

Selects the source of PLL_CLK0 and PLL_CLK1 dedicated IO outputs if selected.  All of the CLKOUT# counter outputs are from the Main PLL.

The following table determines the PLL counter output select:

sel			PLL_CLK0		PLL_CLK1
0000		CLKOUT0		CLKOUT8
0001		CLKOUT1		CLKOUT9
0010		CLKOUT2		CLKOUT10
0011		CLKOUT3		CLKOUT11
0100		CLKOUT4		CLKOUT13
0101		CLKOUT5		CLKOUT14
0110		CLKOUT6		CLKOUT15
0111		CLKOUT7		CLKOUT16
1xxx		VSS				VSS

RW

0x8