ic_fs_spklen

         I2C SS, FS or FM+  spike suppression limit

This register is used to store the duration, measured in l4_sp_clk cycles,
of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. 
The relevant I2C requirement is tSP (table 4) as detailed in the 
I2C Bus Specification. This register must be programmed with a minimum value of 1.
Module Instance Base Address Register Address
i_i2c_emac_0_i2c 0xFFC02400 0xFFC024A0
i_i2c_emac_1_i2c 0xFFC02500 0xFFC025A0
i_i2c_emac_2_i2c 0xFFC02600 0xFFC026A0

Offset: 0xA0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

ic_fs_spklen

RW 0x2

ic_fs_spklen Fields

Bit Name Description Access Reset
7:0 ic_fs_spklen 
This register must be set before any I2C bus transaction can take place to
ensure stable operation. This register sets the duration, measured in l4_sp_clk cycles,
of the longest spike in the SCL or SDA lines that will be filtered out by the spike 
suppression logic.
This register can be written only when the I2C interface is disabled which
corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times
have no effect.
The minimum valid value is 1; hardware prevents values less than this being
written, and if attempted results in 1 being set.
RW 0x2