ic_dma_rdlr

         I2C Receive Data Level Register

Module Instance	Base Address	Register Address
`i_i2c_emac_0_i2c`	`0xFFC02400`	`0xFFC02490`
`i_i2c_emac_1_i2c`	`0xFFC02500`	`0xFFC02590`
`i_i2c_emac_2_i2c`	`0xFFC02600`	`0xFFC02690`

Offset: 0x90

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`										`dmardl` `RW 0x0`

ic_dma_rdlr Fields

Bit	Name	Description	Access	Reset
5:0	`dmardl`	Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. Reset value: 0x0	`RW`	`0x0`

Bit

Name

Description

Access

Reset

5:0

dmardl

Receive Data Level.
This bit field controls the level at which a DMA
request is made by the receive logic. The watermark level =
DMARDL+1; that is, dma_rx_req is generated when the number
of valid data entries in the receive FIFO is equal to or more
than this field value + 1, and RDMAE =1. For instance, when
DMARDL is 0, then dma_rx_req is asserted when 1 or more data
entries are present in the receive FIFO.
Reset value: 0x0

RW

0x0