ic_tx_abrt_source

         I2C Transmit Abort Source Register

This register has 32 bits that indicate the source
of the TX_ABRT bit. Except for Bit 9, this register is
cleared whenever the IC_CLR_TX_ABRT register or the
IC_CLR_INTR register is read. To clear Bit 9, the source
of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must
be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared
(IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).
Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this
bit can be cleared in the same manner as other bits in this
register. If the source of the ABRT_SBYTE_NORSTRT is not fixed
before attempting to clear this bit, Bit 9 clears for one cycle
and is then re-asserted.
Module Instance Base Address Register Address
i_i2c_emac_0_i2c 0xFFC02400 0xFFC02480
i_i2c_emac_1_i2c 0xFFC02500 0xFFC02580
i_i2c_emac_2_i2c 0xFFC02600 0xFFC02680

Offset: 0x80

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

tx_flush_cnt

RO 0x0

rsvd_ic_tx_abrt_source_22to17

RO 0x0

abrt_user_abrt

RO 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

abrt_slvrd_intx

RO 0x0

abrt_slv_arblost

RO 0x0

abrt_slvflush_txfifo

RO 0x0

arb_lost

RO 0x0

abrt_master_dis

RO 0x0

abrt_10b_rd_norstrt

RO 0x0

abrt_sbyte_norstrt

RO 0x0

abrt_hs_norstrt

RO 0x0

abrt_sbyte_ackdet

RO 0x0

abrt_hs_ackdet

RO 0x0

abrt_gcall_read

RO 0x0

abrt_gcall_noack

RO 0x0

abrt_txdata_noack

RO 0x0

abrt_10addr2_noack

RO 0x0

abrt_10addr1_noack

RO 0x0

abrt_7b_addr_noack

RO 0x0

ic_tx_abrt_source Fields

Bit Name Description Access Reset
31:23 tx_flush_cnt 
This field indicates the 
number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. 
It is cleared whenever I2C is disabled.
Reset value: 0x0
Role of the I2C module: Master-Transmitter or Slave-Transmitter
 RO 0x0
22:17 rsvd_ic_tx_abrt_source_22to17 
Reserved
Reset value: 0x0
 RO 0x0
16 abrt_user_abrt 
This is a master-mode-only bit. Master has 
detected the transfer abort (IC_ENABLE[1])
Reset value: 0x0
Role of the I2C module: Master-Transmitter
 RO 0x0
15 abrt_slvrd_intx 
1: When the processor side responds to
a slave mode request for data to be
transmitted to a remote master and user
writes a 1 in CMD (bit 8) of
IC_DATA_CMD register.
Reset value: 0x0
Role of the I2C module: Slave-Transmitter
 RO 0x0
14 abrt_slv_arblost 
1: Slave lost the bus while transmitting
data to a remote master.
IC_TX_ABRT_SOURCE[12] is set at
the same time.
Note: Even though the slave never
'owns' the bus, something could go
wrong on the bus. This is a fail safe
check. For instance, during a data
transmission at the low-to-high
transition of SCL, if what is on the data
bus is not what is supposed to be
transmitted, then the I2C module no
longer owns the bus.
Reset value: 0x0
Role of the I2C module: Slave-Transmitter
 RO 0x0
13 abrt_slvflush_txfifo 
1: Slave has received a read command
and some data exists in the TX FIFO so
the slave issues a TX_ABRT interrupt to
flush old data in TX FIFO.
Reset value: 0x0
Role of the I2C module: Slave-Transmitter
 RO 0x0
12 arb_lost 
1: Master has lost arbitration, or if
IC_TX_ABRT_SOURCE[14] is also
set, then the slave transmitter has lost
arbitration.
Reset value: 0x0
Role of the I2C module: Master-Transmitter
                    or Slave-Transmitter
 RO 0x0
11 abrt_master_dis 
1: User tries to initiate a Master
operation with the Master mode disabled.
Reset value: 0x0
Role of the I2C module: Master-Transmitter
                    or Master-Receiver
 RO 0x0
10 abrt_10b_rd_norstrt 
1: The restart is disabled
(IC_RESTART_EN bit (IC_CON[5]) =0)
and the master sends a read
command in 10-bit addressing mode.
Reset value: 0x0
Role of the I2C module: Master-Receiver
 RO 0x0
9 abrt_sbyte_norstrt 
To clear Bit 9, the source of the
ABRT_SBYTE_NORSTRT must be fixed first;
restart must be enabled (IC_CON[5]=1),
the SPECIAL bit must be cleared (IC_TAR[11]),
or the GC_OR_START bit must be cleared
(IC_TAR[10]). Once the source of the
ABRT_SBYTE_NORSTRT is fixed,
then this bit can be cleared in the same
manner as other bits in this register. If
the source of the ABRT_SBYTE_NORSTRT is not fixed
before attempting to clear this bit, bit 9
clears for one cycle and then gets reasserted.
1: The restart is disabled (IC_RESTART_EN bit
   (IC_CON[5]) =0) and the user is trying to
   send a START Byte.
Reset value: 0x0
Role of the I2C module: Master
 RO 0x0
8 abrt_hs_norstrt 
1: The restart is disabled
(IC_RESTART_EN bit (IC_CON[5]) =0)
and the user is trying to use the
master to transfer data in High Speed
mode.
Reset value: 0x0
Role of the I2C module: Master-Transmitter
                    or Master-Receiver
 RO 0x0
7 abrt_sbyte_ackdet 
1: Master has sent a START Byte and
the START Byte was acknowledged (wrong behavior).
Reset value: 0x0
Role of the I2C module: Master
 RO 0x0
6 abrt_hs_ackdet 
1: Master is in High Speed mode and
the High Speed Master code was
acknowledged (wrong behavior).
Reset value: 0x0
Role of the I2C module: Master
 RO 0x0
5 abrt_gcall_read 
1: The I2C module in master mode sent a
General Call but the user programmed
the byte following the General Call to
be a read from the bus
(IC_DATA_CMD[9] is set to 1).
Reset value: 0x0
Role of the I2C module: Master-Transmitter
 RO 0x0
4 abrt_gcall_noack 
1: The I2C module in master mode sent a
General Call and no slave on the bus
acknowledged the General Call.
Reset value: 0x0
Role of the I2C module: Master-Transmitter
 RO 0x0
3 abrt_txdata_noack 
1: This is a master-mode only bit.
Master has received an
acknowledgement for the address, but
when it sent data byte(s) following the
address, it did not receive an
acknowledge from the remote slave(s).
Reset value: 0x0
Role of the I2C module: Master-Transmitter
 RO 0x0
2 abrt_10addr2_noack 
1: Master is in 10-bit address mode and
the second address byte of the 10-bit
address was not acknowledged by any slave.
Reset value: 0x0
Role of the I2C module: Master-Transmitter
                    or Master-Receiver
 RO 0x0
1 abrt_10addr1_noack 
1: Master is in 10-bit address mode and
the first 10-bit address byte was not
acknowledged by any slave.
Reset value: 0x0
Role of the I2C module: Master-Transmitter
                    or Master-Receiver
 RO 0x0
0 abrt_7b_addr_noack 
1: Master is in 7-bit addressing mode
and the address sent was not
acknowledged by any slave.
Reset value: 0x0
Role of the I2C module: Master-Transmitter
                    or Master-Receiver
 RO 0x0