ic_sda_hold

         I2C SDA Hold Time Length Register

The bits [15:0] of this register are used to control the hold time of SDA during
transmit in both slave and master mode (after SCL goes from HIGH to LOW).
The bits [23:16] of this register are used to extend the SDA transition (if any) 
whenever SCL is HIGH in the receiver in either master or slave mode.
The values in this register are in units of l4_sp_clk period.
This register controls the amount of time delay.
The relevant I2C requirement is thd:DAT as detailed in the I2C
Bus Specification.
Module Instance Base Address Register Address
i_i2c_emac_0_i2c 0xFFC02400 0xFFC0247C
i_i2c_emac_1_i2c 0xFFC02500 0xFFC0257C
i_i2c_emac_2_i2c 0xFFC02600 0xFFC0267C

Offset: 0x7C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

ic_sda_rx_hold

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ic_sda_tx_hold

RW 0x1

ic_sda_hold Fields

Bit Name Description Access Reset
23:16 ic_sda_rx_hold 
Sets the required SDA hold time 
in units of l4_sp_clk period, when the I2C module acts as a receiver.
 RW 0x0
15:0 ic_sda_tx_hold 
Sets the required SDA hold time 
in units of l4_sp_clk period, when the I2C module acts as a transmitter.
 RW 0x1