ic_con

I2C Control Register. This register can be written only when the IC_ENABLE[0] register is set to 0. Writes at other times have no effect.

Module Instance Base Address Register Address
i_i2c_0_i2c 0xFFC02200 0xFFC02200
i_i2c_1_i2c 0xFFC02300 0xFFC02300

Offset: 0x0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

rsvd_ic_con_31to10

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

rsvd_ic_con_31to9

RO 0x0

tx_empty_ctrl

RW 0x0

stop_det_ifaddressed

RW 0x0

ic_slave_disable

RW 0x1

ic_restart_en

RW 0x1

ic_10bitaddr_master

RO 0x1

ic_10bitaddr_slave

RW 0x1

speed

RW 0x2

master_mode

RW 0x1

ic_con Fields

Bit Name Description Access Reset
31:9 rsvd_ic_con_31to9
Reserved bits [31:9] - Read Only
RO 0x0
8 tx_empty_ctrl
This bit controls the generation 
of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.
Reset value: 0x0.
RW 0x0
7 stop_det_ifaddressed
In slave mode:
1:  issues the STOP_DET interrrupt only when it is addressed.
0:  issues the STOP_DET irrespective of whether it’s addressed or not.
Dependencies: This register bit value is applicable in the slave mode only (MASTER_MODE = 1’b0)
Reset value: 0x0
NOTE: During a general call address, this slave does not issue the 
STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if
the slave responds to the general call address by generating ACK.
The STOP_DET interrupt is generated only when the transmitted
address matches the slave address (SAR).
RW 0x0
6 ic_slave_disable
This bit controls whether I2C has its slave disabled.
Once the presetn signal is applied, then
this bit is set to 1. 
When this bit is set (slave is disabled), the I2C module functions only as
a master and does not perform any action that requires a slave.
0: slave is enabled
1: slave is disabled

NOTE: Software should ensure that if this bit is written with 0,
then bit 0 should also be written with a 0.
Value Description
0x0 ENABLE
0x1 DISABLE
RW 0x1
5 ic_restart_en
Determines whether RESTART conditions may be sent when
acting as a master. Some older slaves do not support handling
RESTART conditions; however, RESTART conditions are used in
several DW_apb_i2c operations.
0: disable
1: enable
When RESTART is disabled, the master is prohibited from
performing the following functions:
- Change direction within a transfer (split)
- Send a START BYTE
- High-speed mode operation
- Combined format transfers in 7-bit addressing modes
- Read operation with a 10-bit address
- Send multiple bytes per transfer
By replacing RESTART condition followed by a STOP and a
subsequent START condition, split operations are broken down
into multiple I2C transfers. If the above operations are
performed, it will result in setting bit 6 (TX_ABRT) of the
IC_RAW_INTR_STAT register.
Reset value: 0x1
Value Description
0x0 DISABLE
0x1 ENABLE
RW 0x1
4 ic_10bitaddr_master
The bit is read-only.

0: 7-bit addressing
1: 10-bit addressing

Reset value: 0x1
Value Description
0x0 MSTADDR7BIT
0x1 MSTADDR10BIT
RO 0x1
3 ic_10bitaddr_slave
When acting as a slave, this bit controls whether the I2C module
responds to 7- or 10-bit addresses.
0: 7-bit addressing. The I2C module ignores transactions that
   involve 10-bit addressing; for 7-bit addressing,
   only the lower 7 bits of the IC_SAR register are compared.
1: 10-bit addressing. The I2C module responds to only 10-bit
   addressing transfers that match the full 10 bits of the IC_SAR
   register.
Reset value: 0x1
Value Description
0x0 SLVADDR7BIT
0x1 SLVADDR10BIT
RW 0x1
2:1 speed
These bits control at which speed the I2C operates; its
setting is relevant only if one is operating the I2C module in
master mode. Hardware protects against illegal values being
programmed by software. This register should be programmed
only with a value in the range of 1 to 400 kbits/s; otherwise, hardware updates this register with the value of
400 kbits/s.

1: standard mode (100 kbit/s)
2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)

Reset value: 0x2
Value Description
0x1 STANDARD
0x2 FAST
RW 0x2
0 master_mode
This bit controls whether the I2C master is enabled.
0: master disabled
1: master enabled
Reset value: 0x1
NOTE: Software should ensure that if this bit is written with '1'
then bit 6 should also be written with a '1'.
Value Description
0x0 DISABLE
0x1 ENABLE
RW 0x1