nand_status Address Map

Module Instance Base Address End Address
i_nand_status 0xFFB80400 0xFFB8064F
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Register Offset Width Access Reset Value Description
transfer_mode 0x0 32 RO 0x0 
Current data transfer mode is Main only, Spare only or Main+Spare.
                          This information is per bank.
intr_status0 0x10 32 RW 0x0 
Interrupt status register for bank 0
intr_en0 0x20 32 RW 0x2000 
Enables corresponding interrupt bit in interrupt register
                          for bank 0
page_cnt0 0x30 32 RO 0x0 
Decrementing page count bank 0
err_page_addr0 0x40 32 RO 0x0 
Erred page address bank 0
err_block_addr0 0x50 32 RO 0x0 
Erred block address bank 0
intr_status1 0x60 32 RW 0x0 
Interrupt status register for bank 1
intr_en1 0x70 32 RW 0x2000 
Enables corresponding interrupt bit in interrupt register
                          for bank 1
page_cnt1 0x80 32 RO 0x0 
Decrementing page count bank 1
err_page_addr1 0x90 32 RO 0x0 
Erred page address bank 1
err_block_addr1 0xA0 32 RO 0x0 
Erred block address bank 1
intr_status2 0xB0 32 RW 0x0 
Interrupt status register for bank 2
intr_en2 0xC0 32 RW 0x2000 
Enables corresponding interrupt bit in interrupt register
                          for bank 2
page_cnt2 0xD0 32 RO 0x0 
Decrementing page count bank 2
err_page_addr2 0xE0 32 RO 0x0 
Erred page address bank 2
err_block_addr2 0xF0 32 RO 0x0 
Erred block address bank 2
intr_status3 0x100 32 RW 0x0 
Interrupt status register for bank 3
intr_en3 0x110 32 RW 0x2000 
Enables corresponding interrupt bit in interrupt register
                          for bank 3
page_cnt3 0x120 32 RO 0x0 
Decrementing page count bank 3
err_page_addr3 0x130 32 RO 0x0 
Erred page address bank 3
err_block_addr3 0x140 32 RO 0x0 
Erred block address bank 3