ERRINTEN

         Error Interrupt enable
      
Module Instance Base Address Register Address
ecc_qspi_ecc_registerBlock 0xFF8C8400 0xFF8C8410

Offset: 0x10

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

SERRINTEN

0x0

ERRINTEN Fields

Bit Name Description Access Reset
0 SERRINTEN
This bit is used to enable the single bit error interrupt of ECC RAM system
RW 0x0