emmc_ddr_reg

         EMMC DDR Register
      
Module Instance Base Address Register Address
i_sdmmc_sdmmc 0xFF808000 0xFF80810C

Offset: 0x10C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

half_start_bit

RW 0x0

emmc_ddr_reg Fields

Bit Name Description Access Reset
0 half_start_bit
Control for start bit detection mechanism inside 
DWC_mobile_storage based on duration of start bit; each bit refers to one slot. For eMMC 4.5, start bit can
be:
                                                 ■ Full cycle (HALF_START_BIT = 0)
                                                 ■ Less than one full cycle (HALF_START_BIT = 1)
Set HALF_START_BIT=1 for eMMC 4.5 and above; set to 0 for SD applications.
RW 0x0