cardthrctl
Card Threshold Control Register
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_sdmmc_sdmmc | 0xFF808000 | 0xFF808100 |
Offset: 0x100
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
cardrdthreshold RW 0x0 |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
busy_clr_int_en RW 0x0 |
cardrdthren RW 0x0 |
|||||||||||||
cardthrctl Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 28:16 | cardrdthreshold | Card Read Threshold size; N depends on the FIFO size:
■ N = 27 FIFO_DEPTH is 128
■ N = 26 FIFO_DEPTH is 64
■ N = 25 FIFO_DEPTH is 32
■ N = 24 FIFO_DEPTH is 16
■ N = 23 FIFO_DEPTH is 8
Note: The maximum programmable value of Card Read Threshold size is 512.
|
RW | 0x0 | ||||||
| 1 | busy_clr_int_en | Busy Clear Interrupt generation:
■ 1'b0 - Busy Clear Interrupt disabled
■ 1'b1 - Busy Clear Interrupt enabled
Note: The application can disable this feature if it does not want to wait for a Busy Clear Interrupt. For example, in a multi-card scenario, the application can switch to the other card without waiting for a busy to be completed. In such cases, the application can use the polling method to determine the status of busy. By default this feature is disabled and backward-compatible to the legacy drivers where polling is used.
|
RW | 0x0 | ||||||
| 0 | cardrdthren | Card Read Threshold Enable
■ 1'b0 - Card Read Threshold disabled
■ 1'b1 - Card Read Threshold enabled. Host Controller initiates
Read Transfer only if CardRdThreshold amount of space is
available in receive FIFO.
|
RW | 0x0 |