hcon

         Hardware Configuration Register
Module Instance Base Address Register Address
i_sdmmc_sdmmc 0xFF808000 0xFF808070

Offset: 0x70

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

ac

RO 0x0

aro

RO 0x0

ncd

RO 0x0

scfp

RO 0x1

ihr

RO 0x1

rios

RO 0x0

dmadatawidth

RO 0x1

dmaintf

RO 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

haddrwidth

RO 0xC

hdatawidth

RO 0x1

hbus

RO 0x0

nc

RO 0x0

ct

RO 0x1

hcon Fields

Bit Name Description Access Reset
27 ac 
For 64-bit Address Configuration Only - bit 27
0 - 32 bit addressing supported
1 - 64 bit address supported
 RO 0x0
26 aro 
Area optimized
Value Description
0 NOTOPTFORAREA
RO 0x0
25:24 ncd 
Number of clock dividers less one
Value Description
0 ONEDIV
RO 0x0
23 scfp 
Clock False Path
Value Description
1 SET
RO 0x1
22 ihr 
Implement hold register
Value Description
1 IMPLEMENTED
RO 0x1
21 rios 
FIFO RAM location
Value Description
0 OUTSIDE
RO 0x0
20:18 dmadatawidth 
Encodes bit width of external DMA controller interface. Doesn't apply to the SD/MMC because it has no external DMA controller interface.
Value Description
1 WIDTH32BITS
RO 0x1
17:16 dmaintf 
DMA interface type
Value Description
0 NONE
RO 0x0
15:10 haddrwidth 
Slave bus address width less one
Value Description
12 WIDTH13BITS
RO 0xC
9:7 hdatawidth 
Slave bus data width
Value Description
1 WIDTH32BITS
RO 0x1
6 hbus 
Slave bus type.
Value Description
0 APB
RO 0x0
5:1 nc 
Maximum number of cards less one
Value Description
0 NUMCARD
RO 0x0
0 ct 
Supported card types
Value Description
1 SDMMC
RO 0x1