status

         Status Register
Module Instance Base Address Register Address
i_sdmmc_sdmmc 0xFF808000 0xFF808048

Offset: 0x48

Access: RO

Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

dma_req

RO 0x0

dma_ack

RO 0x0

fifo_count

RO 0x0

response_index

RO 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

response_index

RO 0x0

data_state_mc_busy

RO 0x0

data_busy

RO 0x0

data_3_status

RO 0x1

command_fsm_states

RO 0x0

fifo_full

RO 0x0

fifo_empty

RO 0x1

fifo_tx_watermark

RO 0x1

fifo_rx_watermark

RO 0x0

status Fields

Bit Name Description Access Reset
31 dma_req 
DMA request signal state; either dw_dma_req or ge_dma_req,
depending on DW-DMA or Generic-DMA selection.
 RO 0x0
30 dma_ack 
DMA acknowledge signal state; either dw_dma_ack or
ge_dma_ack, depending on DW-DMA or Generic-DMA selection.
 RO 0x0
29:17 fifo_count 
FIFO count Number of filled locations in FIFO
 RO 0x0
16:11 response_index 
Index of previous response, including any auto-stop sent by core
 RO 0x0
10 data_state_mc_busy 
Data transmit or receive state-machine is busy
Value Description
0 DATASTATENOTBSY
1 DATASTATEBSY
RO 0x0
9 data_busy 
Inverted version of raw selected card_data[0]
                                                 0-card data not busy
                                                 1-card data busy
Value Description
0 CARDNOTBUSY
1 CARDBUSY
RO 0x0
8 data_3_status 
Raw selected card_data[3]; checks whether card is present
                                                 0-card not present
                                                 1-card present
Value Description
0 CARDNOTPRESENT
1 CARDPRESENT
RO 0x1
7:4 command_fsm_states 
Command FSM states:
                                                 0  Idle
                                                 1  Send init sequence
                                                 2  Tx cmd start bit
                                                 3  Tx cmd tx bit
                                                 4  Tx cmd index + arg
                                                 5  Tx cmd crc7
                                                 6  Tx cmd end bit
                                                 7  Rx resp start bit
                                                 8  Rx resp IRQ response
                                                 9  Rx resp tx bit
                                                 10  Rx resp cmd idx
                                                 11  Rx resp data
                                                 12  Rx resp crc7
                                                 13  Rx resp end bit
                                                 14  Cmd path wait NCC
                                                 15  Wait; CMD-to-response turnaround
NOTE: The command FSM state is represented using 19 bits. The STATUS Register(7:4) has 4 bits to represent the command FSM states. Using these 4 bits, only 16 states can be represented. Thus three states cannot be represented in the STATUS(7:4) register. The three states that are not represented in the STATUS Register(7:4) are:
 * Bit 16  Wait for CCS
 * Bit 17  Send CCSD
 * Bit 18  Boot Mode
Due to this, while command FSM is in “Wait for CCS state” or “Send CCSD” or “Boot Mode”, the Status register indicates status as 0 for the bit field 7:4.
Value Description
0 IDLEANDOTHERS
1 SENDINITSEQ
2 TXCMDSTART
3 TXCMDTXBIT
4 TXCMDINDXARG
5 TXCMDCRC7
6 TXCMDEND
7 RXRESPSTART
8 RXRESPIRQ
9 RXRESPTX
10 RXRESPCMDIDX
11 RXRESPDATA
12 RXRESPCRC7
13 RXRESPEND
14 CMDPATHWAIT
15 WAITCMDTURN
RO 0x0
3 fifo_full 
FIFO is full status
Value Description
0 FIFONOTFULL
1 FIFOFULL
RO 0x0
2 fifo_empty 
FIFO is empty status
Value Description
0 FIFONOTEMPTY
1 FIFOEMPTY
RO 0x1
1 fifo_tx_watermark 
FIFO reached Transmit watermark level; not qualified with data
transfer.
Value Description
0 NOTXWATERMARK
1 TXWATERMARK
RO 0x1
0 fifo_rx_watermark 
FIFO reached Receive watermark level; not qualified with data
transfer.
Value Description
0 RXWATERMARK
1 NORXWATERMARK
RO 0x0