cmd

         Command Register
      
Module Instance Base Address Register Address
i_sdmmc_sdmmc 0xFF808000 0xFF80802C

Offset: 0x2C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

start_cmd

RW 0x0

Reserved

use_hold_reg

RW 0x1

volt_switch

RW 0x0

boot_mode

RW 0x0

disable_boot

RW 0x0

expect_boot_ack

RW 0x0

enable_boot

RW 0x0

ccs_expected

RW 0x0

read_ceata_device

RW 0x0

update_clock_registers_only

RW 0x0

card_number

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

send_initialization

RW 0x0

stop_abort_cmd

RW 0x0

wait_prvdata_complete

RW 0x0

send_auto_stop

RW 0x0

transfer_mode

RW 0x0

read_write

RW 0x0

data_expected

RW 0x0

check_response_crc

RW 0x0

response_length

RW 0x0

response_expect

RW 0x0

cmd_index

RW 0x0

cmd Fields

Bit Name Description Access Reset
31 start_cmd
Start command. Once command is taken by CIU, bit is cleared.
When bit is set, host should not attempt to write to any command registers. If write is attempted, hardware lock error is set in raw interrupt register.
Once command is sent and response is received from SD_MMC_CEATA cards, Command Done bit is set in raw interrupt
register.
Value Description
0 NOSTART
1 START
RW 0x0
29 use_hold_reg
Use Hold Register
                                                 0 - CMD and DATA sent to card bypassing HOLD Register
                                                 1 - CMD and DATA sent to card through the HOLD Register
Value Description
0 BYPASS
1 NOBYPASS
RW 0x1
28 volt_switch
Voltage switch bit
                                                 0 - No voltage switching
                                                 1 - Voltage switching enabled; must be set for CMD11 only
Value Description
0 NOVOLTSW
1 VOLTSW
RW 0x0
27 boot_mode
Boot Mode
                                                 0 - Mandatory Boot operation
                                                 1 - Alternate Boot operation
Value Description
0 MANDATORY
1 ALTERNATE
RW 0x0
26 disable_boot
Disable Boot. When software sets this bit along with start_cmd, CIU terminates the boot operation. Do NOT set disable_boot and enable_boot together.
Value Description
0 NOTERMBOOT
1 TERMBOOT
RW 0x0
25 expect_boot_ack
Expect Boot Acknowledge. When Software sets this bit along with
enable_boot, CIU expects a boot acknowledge start pattern of 0-1-0 from the selected card.
Value Description
0 NOBOOTACK
1 BOOTACK
RW 0x0
24 enable_boot
Enable Bootthis bit should be set only for mandatory boot mode.
When Software sets this bit along with start_cmd, CIU starts the boot sequence for the corresponding card by asserting the CMD line low. Do NOT set disable_boot and enable_boot together.
Value Description
0 DISABLED
1 ENABLED
RW 0x0
23 ccs_expected
0-Interrupts are not enabled in CE-ATA device (nIEN = 1 in
                                                   ATA control register), or command does not expect CCS 
                                                   from device
                                                 1-Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK 
                                                   command expects command completion signal from CE-ATA device
If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit.DWC_mobile_storage sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked.
Value Description
0 DISABLED
1 ENABLED
RW 0x0
22 read_ceata_device
0-Host is not performing read access (RW_REG or RW_BLK)
                                                   towards CE-ATA device
                                                 1-Host is performing read access (RW_REG or RW_BLK)
                                                   towards CE-ATA device
Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers.Maximum value of I/O transmission delay can be no less than 10 seconds. DWC_mobile_storage should not indicate read data timeout while waiting for data from CE-ATA device.
Value Description
0 NORD
1 RD
RW 0x0
21 update_clock_registers_only
0-Normal command sequence
                                                 1-Do not send commands, just update clock register value into
                                                   card clock domain
Following register values transferred into card clock domain: CLKDIV, CLRSRC, CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode); provided in order to change clock frequency or stop clock without having to send command to cards.During normal command sequence, when update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE,BLKSIZ, BYTCNT. CIU uses new register values for new command sequence to card(s).When bit is set, there are no Command Done interrupts because no
command is sent to SD_MMC_CEATA cards.
Value Description
0 NORMCMD
1 UPDATCLKREG
RW 0x0
20:16 card_number
Card number in use. Represents physical slot number of card being
accessed. In MMC-Ver3.3-only mode, up to 30 cards are supported; in SD-only mode, up to 16 cards are supported. Registered version of this is reflected on dw_dma_card_num and ge_dma_card_num ports, which can be used to create separate DMA requests, if needed.
In addition, in SD mode this is used to mux or demux signals from selected card because each card is interfaced to
DWC_mobile_storage by separate bus.
RW 0x0
15 send_initialization
0-Do not send initialization sequence (80 clocks of 1) before
                                                   sending this command
                                                 1-Send initialization sequence before sending this command
After power on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. This bit should not be set for either of the boot modes (alternate or mandatory).
Value Description
0 NOINIT
1 INIT
RW 0x0
14 stop_abort_cmd
0-Neither stop nor abort command to stop current data transfer
                                                   in progress. If abort is sent to function-number currently
                                                   selected or not in data-transfer mode, then bit should be set
                                                   to 0.
                                                 1-Stop or abort command intended to stop current data transfer
                                                   in progress.
When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. This is also applicable for Boot mode transfers. To Abort boot mode, this bit should be set along with CMD[26] = disable_boot.
Value Description
0 NOSTOPABRT
1 STOPABRT
RW 0x0
13 wait_prvdata_complete
0-Send command at once, even if previous data transfer has not
                                                   completed
                                                 1-Wait for previous data transfer completion before sending
                                                   command
The wait_prvdata_complete = 0 option typically used to query status of card during data transfer or to stop current data transfer;card_number should be same as in previous command.
Value Description
0 NOWAIT
1 WAIT
RW 0x0
12 send_auto_stop
0-No stop command sent at end of data transfer
                                                 1-Send stop command at end of data transfer
When set, DWC_mobile_storage sends stop command to SD_MMC_CEATA cards at end of data transfer.
 * when send_auto_stop bit should be set, since some data
   transfers do not need explicit stop commands
 * open-ended transfers that software should explicitly send to
   stop command
Additionally, when “resume” is sent to resume  suspended memory access of SD-Combo card  bit should be set correctly if suspended data transfer needs send_auto_stop.Don't care if no data expected from card.
Value Description
0 NOSEND
1 SEND
RW 0x0
11 transfer_mode
0-Block data transfer command
                                                 1-Stream data transfer command
                                                 Don’t care if no data expected.
Value Description
0 BLK
1 STR
RW 0x0
10 read_write
0-Read from card
                                                 1-Write to card
                                                 Don’t care if no data expected from card.
Value Description
0 RD
1 WR
RW 0x0
9 data_expected
0-No data transfer expected (read/write)
                                                 1-Data transfer expected (read/write)
Value Description
0 NODATXFEREXP
1 DATAXFEREXP
RW 0x0
8 check_response_crc
0-Do not check response CRC
                                                 1-Check response CRC
Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller.
Value Description
0 NOCHK
1 CHK
RW 0x0
7 response_length
0-Short response expected from card
                                                 1-Long response expected from card
Value Description
0 SHORT
1 LONG
RW 0x0
6 response_expect
0-No response expected from card
                                                 1-Response expected from card
Value Description
0 RESP
1 NORESP
RW 0x0
5:0 cmd_index
Command index
RW 0x0