intmask
Interrupt Mask Register
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_sdmmc_sdmmc | 0xFF808000 | 0xFF808024 |
Offset: 0x24
Access: RW
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
sdio_int_mask RW 0x0 |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ebe RW 0x0 |
acd RW 0x0 |
sbe RW 0x0 |
hle RW 0x0 |
frun RW 0x0 |
hto RW 0x0 |
drt RW 0x0 |
rto RW 0x0 |
dcrc RW 0x0 |
rcrc RW 0x0 |
rxdr RW 0x0 |
txdr RW 0x0 |
dto RW 0x0 |
cmd RW 0x0 |
re RW 0x0 |
cd RW 0x0 |
intmask Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31:16 | sdio_int_mask | Mask SDIO interrupts One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0 masks an interrupt, and 1 enables an interrupt. In MMC-Ver3.3-only mode, these bits are always 0.
|
RW | 0x0 | ||||||
| 15 | ebe | Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.
|
RW | 0x0 | ||||||
| 14 | acd | Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.
|
RW | 0x0 | ||||||
| 13 | sbe | Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.
|
RW | 0x0 | ||||||
| 12 | hle | Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.
|
RW | 0x0 | ||||||
| 11 | frun | Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.
|
RW | 0x0 | ||||||
| 10 | hto | Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.
|
RW | 0x0 | ||||||
| 9 | drt | Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.
|
RW | 0x0 | ||||||
| 8 | rto | Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.
|
RW | 0x0 | ||||||
| 7 | dcrc | Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.
|
RW | 0x0 | ||||||
| 6 | rcrc | Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.
|
RW | 0x0 | ||||||
| 5 | rxdr | Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.
|
RW | 0x0 | ||||||
| 4 | txdr | Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.
|
RW | 0x0 | ||||||
| 3 | dto | Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.
|
RW | 0x0 | ||||||
| 2 | cmd | Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.
|
RW | 0x0 | ||||||
| 1 | re | Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.
|
RW | 0x0 | ||||||
| 0 | cd | Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.
|
RW | 0x0 |