gmacgrp_mmc_transmit_interrupt_mask
Register 68 (MMC Transmit Interrupt Mask Register)
The MMC Transmit Interrupt Mask register maintains the masks for the interrupts generated when the transmit statistic counters reach half of their maximum value or maximum value. This register is 32-bits wide.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_emac_emac0 | 0xFF800000 | 0xFF800110 |
| i_emac_emac1 | 0xFF802000 | 0xFF802110 |
| i_emac_emac2 | 0xFF804000 | 0xFF804110 |
Offset: 0x110
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
reserved_31_26 RO 0x0 |
txosizegfim RW 0x0 |
txvlangfim RW 0x0 |
txpausfim RW 0x0 |
txexdeffim RW 0x0 |
txgfrmim RW 0x0 |
txgoctim RW 0x0 |
txcarerfim RW 0x0 |
txexcolfim RW 0x0 |
txlatcolfim RW 0x0 |
txdeffim RW 0x0 |
|||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
txmcolgfim RW 0x0 |
txscolgfim RW 0x0 |
txuflowerfim RW 0x0 |
txbcgbfim RW 0x0 |
txmcgbfim RW 0x0 |
txucgbfim RW 0x0 |
tx1024tmaxoctgbfim RW 0x0 |
tx512t1023octgbfim RW 0x0 |
tx256t511octgbfim RW 0x0 |
tx128t255octgbfim RW 0x0 |
tx65t127octgbfim RW 0x0 |
tx64octgbfim RW 0x0 |
txmcgfim RW 0x0 |
txbcgfim RW 0x0 |
txgbfrmim RW 0x0 |
txgboctim RW 0x0 |
gmacgrp_mmc_transmit_interrupt_mask Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31:26 | reserved_31_26 | Reserved |
RO | 0x0 | ||||||
| 25 | txosizegfim | MMC Transmit Oversize Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 24 | txvlangfim | MMC Transmit VLAN Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txvlanframes_g counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 23 | txpausfim | MMC Transmit Pause Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txpauseframes counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 22 | txexdeffim | MMC Transmit Excessive Deferral Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 21 | txgfrmim | MMC Transmit Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txframecount_g counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 20 | txgoctim | MMC Transmit Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 19 | txcarerfim | MMC Transmit Carrier Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 18 | txexcolfim | MMC Transmit Excessive Collision Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 17 | txlatcolfim | MMC Transmit Late Collision Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 16 | txdeffim | MMC Transmit Deferred Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 15 | txmcolgfim | MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 14 | txscolgfim | MMC Transmit Single Collision Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 13 | txuflowerfim | MMC Transmit Underflow Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 12 | txbcgbfim | MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 11 | txmcgbfim | MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 10 | txucgbfim | MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txunicastframes_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 9 | tx1024tmaxoctgbfim | MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 8 | tx512t1023octgbfim | MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 7 | tx256t511octgbfim | MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 6 | tx128t255octgbfim | MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 5 | tx65t127octgbfim | MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 4 | tx64octgbfim | MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 3 | txmcgfim | MMC Transmit Multicast Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastframes_g counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 2 | txbcgfim | MMC Transmit Broadcast Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 1 | txgbfrmim | MMC Transmit Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the txframecount_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 0 | txgboctim | MMC Transmit Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 |