fpga_bridge_soc2fpga128 Address Map

This address space is allocated for the configurable-width, high-performance master interface to the FPGA fabric. For more information about the HPS-to-FPGA bridges, refer to the HPS-FPGA Bridges chapter in the Arria 10 Hard Processor System Technical Reference Manual.

Module Instance	Base Address	End Address
`i_fpga_bridge_soc2fpga128`	`0xC0000000`	`0xFBFFFFFF`