phy_dqs_timing_reg


Module Instance	Base Address	Register Address
`i_sys_mgr__sysmgr_csr__10d12000__core__SEG_L4_SHR_SystemManager_0x0_0x1000`	`0x10D12000`	`0x10D12110`

Size: 32

Offset: 0x110

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_7` `RO 0x0`								`dqs_clkperiod_delay` `RW 0x0`	`Reserved_6` `RO 0x0`		`use_phony_dqs` `RW 0x1`	`Reserved_5` `RO 0x0`			`phony_dqs_sel` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`dqs_select_tsel_start` `RW 0x0`				`dqs_select_tsel_end` `RW 0x0`				`dqs_select_oe_start` `RW 0x0`				`dqs_select_oe_end` `RW 0x4`

phy_dqs_timing_reg Fields


Bit	Name	Description	Access	Reset
31:24	`Reserved_7`	Reserved bitfield added by Magillem	`RO`	`0x0`
23	`dqs_clkperiod_delay`		`RW`	`0x0`
22:21	`Reserved_6`	Reserved bitfield added by Magillem	`RO`	`0x0`
20	`use_phony_dqs`		`RW`	`0x1`
19:17	`Reserved_5`	Reserved bitfield added by Magillem	`RO`	`0x0`
16	`phony_dqs_sel`		`RW`	`0x0`
15:12	`dqs_select_tsel_start`		`RW`	`0x0`
11:8	`dqs_select_tsel_end`		`RW`	`0x0`
7:4	`dqs_select_oe_start`		`RW`	`0x0`
3:0	`dqs_select_oe_end`		`RW`	`0x4`