i3c_slv_ctrl_1


Module Instance	Base Address	Register Address
`i_sys_mgr__sysmgr_csr__10d12000__core__SEG_L4_SHR_SystemManager_0x0_0x1000`	`0x10D12000`	`0x10D12148`

Size: 32

Offset: 0x148

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_6` `RO 0x0`	`static_addr` `RW 0x0`							`inst_id` `RW 0x0`				`Reserved_4` `RO 0x0`	`slv_clk_data_turn_time` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_3` `RO 0x0`	`slv_max_wr_speed` `RW 0x0`			`Reserved_2` `RO 0x0`	`slv_max_rd_speed` `RW 0x0`			`slv_dcr` `RW 0x0`

i3c_slv_ctrl_1 Fields


Bit	Name	Description	Access	Reset
31	`Reserved_6`	Reserved bitfield added by Magillem	`RO`	`0x0`
30:24	`static_addr`		`RW`	`0x0`
23:20	`inst_id`		`RW`	`0x0`
19	`Reserved_4`	Reserved bitfield added by Magillem	`RO`	`0x0`
18:16	`slv_clk_data_turn_time`		`RW`	`0x0`
15	`Reserved_3`	Reserved bitfield added by Magillem	`RO`	`0x0`
14:12	`slv_max_wr_speed`		`RW`	`0x0`
11	`Reserved_2`	Reserved bitfield added by Magillem	`RO`	`0x0`
10:8	`slv_max_rd_speed`		`RW`	`0x0`
7:0	`slv_dcr`		`RW`	`0x0`