fpgaintf_en_1 

         Used to disable individual interfaces between the FPGA and HPS.
This register is reset only on a cold reset (ignores warm reset).
Module Instance Base Address Register Address
i_sys_mgr__sysmgr_csr__10d12000__core__SEG_L4_SHR_SystemManager_0x0_0x1000 0x10D12000 0x10D12068

Size: 32

Offset: 0x68

Access: RW

Access mode: PRIVILEGEMODE | SECURE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_5

RO 0x0

ctmtrigger

RW 0x1

Reserved_4

RO 0x0

stmevent

RW 0x1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_3

RO 0x0

dbgapb

RW 0x1

Reserved_2

RO 0x0

traceout

RW 0x1

Reserved_1

RO 0x0

tracein

RW 0x0

fpgaintf_en_1 Fields

Bit Name Description Access Reset
31:25 Reserved_5 
Reserved bitfield added by Magillem
 RO 0x0
24 ctmtrigger 
Used to disable the FPGA Fabric from sending triggers to HPS debug logic.  Note that this doesn't prevent the HPS debug logic from sending triggers to the FPGA Fabric.
Value Description
0 Disable
1 Enable
RW 0x1
23:17 Reserved_4 
Reserved bitfield added by Magillem
 RO 0x0
16 stmevent 
Used to disable the STM event interface. This interface allows logic in the FPGA fabric to trigger events to the STM debug module in the HPS.
Value Description
0 Disable
1 Enable
RW 0x1
15:9 Reserved_3 
Reserved bitfield added by Magillem
 RO 0x0
8 dbgapb 
Used to disable the debug APB interface. This interface allows the HPS debug logic to communicate with debug APB slaves in the FPGA fabric.
Value Description
0 Disable
1 Enable
RW 0x1
7:5 Reserved_2 
Reserved bitfield added by Magillem
 RO 0x0
4 traceout 
Gates the isolator of CoreSight
Value Description
0 Disable
1 Enable
RW 0x1
3:1 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
0 tracein 
Gates the isolator of TPIU
Value Description
0 Disable
1 Enable
RW 0x0