ecc_intmask_set

         Write 1 to set a specific modules interrupt mask.
Reads should not return an error, but the actual read value is "Undefined" .


Module Instance	Base Address	Register Address
`i_sys_mgr__sysmgr_csr__10d12000__core__SEG_L4_SHR_SystemManager_0x0_0x1000`	`0x10D12000`	`0x10D12094`

Size: 32

Offset: 0x94

Access: WO

Access mode: PRIVILEGEMODE | SECURE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_18` `WO 0x0`													`dma1` `RW 0x0`	`ddr1` `RW 0x0`	`ddr0` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`sdmmcb` `RW 0x0`	`sdmmca` `RW 0x0`	`nand_rd` `RW 0x0`	`usb31_ram2` `RW 0x0`	`usb31_ram1` `RW 0x0`	`dma0` `RW 0x0`	`tsn2_tx` `RW 0x0`	`tsn2_rx` `RW 0x0`	`tsn1_tx` `RW 0x0`	`tsn1_rx` `RW 0x0`	`tsn0_tx` `RW 0x0`	`tsn0_rx` `RW 0x0`	`usb31_ram0` `RW 0x0`	`usb0` `RW 0x0`	`ocram` `RW 0x0`	`Reserved_0` `WO 0x0`

ecc_intmask_set Fields


Bit	Name	Description	Access	Reset
31:19	`Reserved_18`	Reserved bitfield added by Magillem	`WO`	`0x0`
18	`dma1`		`RW`	`0x0`
17	`ddr1`		`RW`	`0x0`
16	`ddr0`		`RW`	`0x0`
15	`sdmmcb`		`RW`	`0x0`
14	`sdmmca`		`RW`	`0x0`
13	`nand_rd`		`RW`	`0x0`
12	`usb31_ram2`		`RW`	`0x0`
11	`usb31_ram1`		`RW`	`0x0`
10	`dma0`		`RW`	`0x0`
9	`tsn2_tx`		`RW`	`0x0`
8	`tsn2_rx`		`RW`	`0x0`
7	`tsn1_tx`		`RW`	`0x0`
6	`tsn1_rx`		`RW`	`0x0`
5	`tsn0_tx`		`RW`	`0x0`
4	`tsn0_rx`		`RW`	`0x0`
3	`usb31_ram0`		`RW`	`0x0`
2	`usb0`		`RW`	`0x0`
1	`ocram`		`RW`	`0x0`
0	`Reserved_0`	Reserved bitfield added by Magillem	`WO`	`0x0`