hdsken 

         This register allows software to control whether or not to perform a handshake with certain peripherals before issuing a reset. These bits are cleared on a cold reset. If these bits are not set, writing to the "hdskreq" register to request a software-triggered handshake will not perform the handshake. 
If the peripheral is being held in reset, then the handshake will be skipped, regardless of whether the handshake enable bit is set or not.
Module Instance Base Address Register Address
i_rst_mgr__rstmgr_csr__10d11000__rstmgr__SEG_L4_SHR_ResetManager_0x0_0x1000 0x10D11000 0x10D11010

Size: 32

Offset: 0x10

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_9

RO 0x3FFF

debug_l3noc

RW 0x1

l3noc_dbg

RW 0x1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_7

RO 0x7

f2soc_flush

RW 0x1

f2sdram_flush

RW 0x1

soc2fpga_flush

RW 0x1

lwsoc2fpga_flush

RW 0x1

Reserved_3

RO 0x1F

etrstallen

RW 0x1

fpgahsen

RW 0x0

Reserved_1

RO 0x1

emif_flush

RW 0x1

hdsken Fields

Bit Name Description Access Reset
31:18 Reserved_9 
Reserved bitfield added by Magillem
 RO 0x3FFF
17 debug_l3noc 
This field controls whether to perform handshake with L3 NOC before asserting the csdap_rst or/and dbg_rst. If set to 1, the Reset Manager makes a request to the L3 NOC before issuing a reset. If set to 0, the handshake is not performed.
This handshake is performed when CS DAP or/and DBG is getting reset but NOC is not getting reset.
 RW 0x1
16 l3noc_dbg 
This field controls whether to perform handshake with L3 NOC before issuing a reset. If set to 1, the Reset Manager makes a request to the L3 NOC before issuing a reset. If set to 0, the handshake is not performed. 
This handshake is performed when NOC is getting reset but debug and dap are not getting reset
 RW 0x1
15:13 Reserved_7 
Reserved bitfield added by Magillem
 RO 0x7
12 f2soc_flush 
This field controls whether to fence and drain traffic on the MPFE F2S ACE-lite port before resetting the HPS. If set to 1, the Reset Manager makes a handshake request to the MPFE NoC before issuing a reset. If set to 0, the handshake is not performed
 RW 0x1
11 f2sdram_flush 
This field controls whether to fence and drain traffic on the MPFE F2SDRAM AXI4 port before resetting the HPS. If set to 1, the Reset Manager makes a handshake request to the MPFE NoC before issuing a reset. If set to 0, the handshake is not performed.
 RW 0x1
10 soc2fpga_flush 
This field controls whether to fence and drain traffic on the SOC2FPGA port before resetting the HPS. If set to 1, the Reset Manager makes a handshake request to the PSS NoC before issuing a reset. If set to 0, the handshake is not performed.
 RW 0x1
9 lwsoc2fpga_flush 
This field controls whether to fence and drain traffic on the LWSOC2FPGA port before resetting the HPS. If set to 1, the Reset Manager makes a handshake request to the PSS NoC before issuing a reset. If set to 0, the handshake is not performed
 RW 0x1
8:4 Reserved_3 
Reserved bitfield added by Magillem
 RO 0x1F
3 etrstallen 
Software writes this field 1 to request to the ETR that it stalls its AXI master to the L3 Interconnect.
This field controls whether the hardware should perform a handhshake with the ETR before issuing a reset. If set to 1, the Reset Manager handshakes with the ETR.  If set to 0, the handshake is not performed.
 RW 0x1
2 fpgahsen 
This field controls whether to perform handshake with FPGA before issuing a reset. If set to 1, the Reset Manager makes a request to the FPGA before issuing a reset. If set to 0, the handshake is not performed.
 RW 0x0
1 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x1
0 emif_flush 
This field controls whether to perform handshake with the SDRAM memory interface before issuing a reset. If set to 1, the Reset Manager makes a request to the SDRAM memory interface before issuing a reset. If set to 0, the handshake is not performed.
 RW 0x1