timings2 

         Global timings configuration - register 2.
Module Instance Base Address Register Address
i_nand__reg_apb__10b80000__rf_minictrl_regs__SEG_L4_MP_nand_s_0x0_0x10000 0x10B81000 0x10B8102C

Size: 32

Offset: 0x2C

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_3

RO 0x0

tFEAT

RW 0x3FF

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_2

RO 0x0

CS_hold_time

RW 0x3F

Reserved_1

RO 0x0

CS_setup_time

RW 0x3F

timings2 Fields

Bit Name Description Access Reset
31:26 Reserved_3 
Reserved bitfield added by Magillem
 RO 0x0
25:16 tFEAT 
Signifies the number of Minicontroller clock cycles (nf_clk) that should be introduced after a Set Features command and Reset command (since this command change the work mode of the NAND Flash device). For most devices this register refers to device timing parameter tITC. For the devices which do not have this timing that is . does not have timing mode change feature the tWB timing should be defined in this field. It is valid only for Set Features run in PIO mode and Reset command for every controller mode.
 RW 0x3FF
15:14 Reserved_2 
Reserved bitfield added by Magillem
 RO 0x0
13:8 CS_hold_time 
Number of Minicontroller clock cycles (nf_clk) required for meeting chip select high time. This register refers to device timing parameter tCEH. Some legacy devices may have a tWHC (WE# high to CE# low) timing requirement. To meet this requirement the higher value from the tCEH/tWHC should be written to this field.
 RW 0x3F
7:6 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
5:0 CS_setup_time 
              Number of Minicontroller clock cycles (nf_clk) required for meeting chip select setup time.
              This register refers to device chip enable setup timing parameter tCS. Some devices may define more than one tCS timing parameters.
              Controller implements one timing for all sequences. It has to be programmed accordingly to the performed sequence.
              In NV-DDR mode this timing should be consistent with tRR timing parameter.
RW 0x3F