timings0
Global timings configuration - register 0.
Module Instance | Base Address | Register Address |
---|---|---|
i_nand__reg_apb__10b80000__rf_minictrl_regs__SEG_L4_MP_nand_s_0x0_0x10000
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0x10B81000
|
0x10B81024
|
Size: 32
Offset: 0x24
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields | |||||||||||||||
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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timings0 Fields
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
31:24 |
tADL
|
Signifies the number of clock cycles that should be introduced between an address to a data input cycle. The timing value follows tADL. The number programmed in this register should be in terms of Minicontroller clock cycles (nf_clk) that would be required to satisfy the time. |
RW
|
0xFF
|
23:16 |
tCCS
|
Timing parameter for minimum change column setup time. The timing value follows tCCS (tWHR2 for Toggle DDR devices). The number programmed in this register should be in terms of Minicontroller clock cycles (nf_clk) that would be required to satisfy the time. |
RW
|
0xFF
|
15:8 |
tWHR
|
Timing parameter between we high to re low. The timing value follows tWHR. The number programmed in this register should be in terms of Minicontroller clock cycles (nf_clk) that would be required to satisfy the time. Some Toggle Mode devices requires to meet tWHR2 timing after 00h command - to meet this requirement this field (tWHR) need to be set to the value that satisfy tWHR2. |
RW
|
0xFF
|
7:0 |
tRHW
|
Timing parameter between re high to we low. The timing value follows tRHW. The number programmed in this register should be in terms of Minicontroller clock cycles (nf_clk) that would be required to satisfy the time. |
RW
|
0xFF
|