DAINTMSK 

         Device All Endpoints Interrupt Mask Register
Module Instance Base Address Register Address
i_usbotg_0__usb_csr__10b00000__DWC_otg_intreg__SEG_L4_AHB_USB0_0x0_0x40000 0x10B00000 0x10B0081C

Size: 32

Offset: 0x81C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

OutEPMsk15

RW 0x0

OutEPMsk14

RW 0x0

OutEPMsk13

RW 0x0

OutEPMsk12

RW 0x0

OutEPMsk11

RW 0x0

OutEPMsk10

RW 0x0

OutEPMsk9

RW 0x0

OutEPMsk8

RW 0x0

OutEPMsk7

RW 0x0

OutEPMsk6

RW 0x0

OutEPMsk5

RW 0x0

OutEPMsk4

RW 0x0

OutEPMsk3

RW 0x0

OutEPMsk2

RW 0x0

OutEPMsk1

RW 0x0

OutEPMsk0

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

InEpMsk15

RW 0x0

InEpMsk14

RW 0x0

InEpMsk13

RW 0x0

InEpMsk12

RW 0x0

InEpMsk11

RW 0x0

InEpMsk10

RW 0x0

InEpMsk9

RW 0x0

InEpMsk8

RW 0x0

InEpMsk7

RW 0x0

InEpMsk6

RW 0x0

InEpMsk5

RW 0x0

InEpMsk4

RW 0x0

InEpMsk3

RW 0x0

InEpMsk2

RW 0x0

InEpMsk1

RW 0x0

InEpMsk0

RW 0x0

DAINTMSK Fields

Bit Name Description Access Reset
31 OutEPMsk15 
OUT Endpoint 15 Interrupt mask Bit
 RW 0x0
30 OutEPMsk14 
OUT Endpoint 14 Interrupt mask Bit
 RW 0x0
29 OutEPMsk13 
OUT Endpoint 13 Interrupt mask Bit
 RW 0x0
28 OutEPMsk12 
OUT Endpoint 12 Interrupt mask Bit
 RW 0x0
27 OutEPMsk11 
OUT Endpoint 11 Interrupt mask Bit
 RW 0x0
26 OutEPMsk10 
OUT Endpoint 10 Interrupt mask Bit
 RW 0x0
25 OutEPMsk9 
OUT Endpoint 9 Interrupt mask Bit
 RW 0x0
24 OutEPMsk8 
OUT Endpoint 8 Interrupt mask Bit
 RW 0x0
23 OutEPMsk7 
OUT Endpoint 7 Interrupt mask Bit
 RW 0x0
22 OutEPMsk6 
OUT Endpoint 6 Interrupt mask Bit
 RW 0x0
21 OutEPMsk5 
OUT Endpoint 5 Interrupt mask Bit
 RW 0x0
20 OutEPMsk4 
OUT Endpoint 4 Interrupt mask Bit
 RW 0x0
19 OutEPMsk3 
OUT Endpoint 3 Interrupt mask Bit
 RW 0x0
18 OutEPMsk2 
OUT Endpoint 2 Interrupt mask Bit
 RW 0x0
17 OutEPMsk1 
OUT Endpoint 1 Interrupt mask Bit
 RW 0x0
16 OutEPMsk0 
OUT Endpoint 0 Interrupt mask Bit
Value Description
0x0 OUT Endpoint 0 Interrupt mask
0x1 No Interrupt mask
RW 0x0
15 InEpMsk15 
IN Endpoint 15 Interrupt mask Bit
 RW 0x0
14 InEpMsk14 
IN Endpoint 14 Interrupt mask Bit
 RW 0x0
13 InEpMsk13 
IN Endpoint 13 Interrupt mask Bit
 RW 0x0
12 InEpMsk12 
IN Endpoint 12 Interrupt mask Bit
 RW 0x0
11 InEpMsk11 
IN Endpoint 11 Interrupt mask Bit
 RW 0x0
10 InEpMsk10 
IN Endpoint 10 Interrupt mask Bit
 RW 0x0
9 InEpMsk9 
IN Endpoint 9 Interrupt mask Bit
 RW 0x0
8 InEpMsk8 
IN Endpoint 8 Interrupt mask Bit
 RW 0x0
7 InEpMsk7 
IN Endpoint 7 Interrupt mask Bit
 RW 0x0
6 InEpMsk6 
IN Endpoint 6 Interrupt mask Bit
 RW 0x0
5 InEpMsk5 
IN Endpoint 5 Interrupt mask Bit
 RW 0x0
4 InEpMsk4 
IN Endpoint 4 Interrupt mask Bit
 RW 0x0
3 InEpMsk3 
IN Endpoint 3 Interrupt mask Bit
 RW 0x0
2 InEpMsk2 
IN Endpoint 2 Interrupt mask Bit
 RW 0x0
1 InEpMsk1 
IN Endpoint 1 Interrupt mask Bit
 RW 0x0
0 InEpMsk0 
IN Endpoint 0 Interrupt mask Bit
Value Description
0x0 IN Endpoint 0 Interrupt mask
0x1 No Interrupt mask
RW 0x0