INTR_FORCE
Interrupt Force Enable Register
Individual interrupts can be forcefully triggered if corresponding Force Enable bit is set, provided
the corresponding bit in the INTR_STATUS_EN register is set.
| Module Instance | Base Address | Register Address |
|---|---|---|
i_i3c_secondary_master__i3c_s_apb_slv__10da1000__DWC_mipi_i3c_block__SEG_L4_SP_i3c1_0x0_0x1000
|
0x10DA1000
|
0x10DA1048
|
Size: 32
Offset: 0x48
Access: WO
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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INTR_FORCE Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 31:14 |
Reserved_13
|
Reserved bitfield added by Magillem |
WO
|
0x0
|
| 13 |
BUSOWNER_UPDATED_FORCE_EN
|
Bus owner Updated Force Enable |
WO
|
0x0
|
| 12 |
IBI_UPDATED_FORCE_EN
|
IBI Updated Force Enable This field is used in slave mode of operation. |
WO
|
0x0
|
| 11 |
READ_REQ_FORCE_EN
|
Read Request Received Force Enable This field is used in slave mode of operation. |
WO
|
0x0
|
| 10 |
DEFSLV_FORCE_EN
|
Define Slave CCC Received Force Enable |
WO
|
0x0
|
| 9 |
TRANSFER_ERR_FORCE_EN
|
Transfer Error Force Enable |
WO
|
0x0
|
| 8 |
DYN_ADDR_ASSGN_FORCE_EN
|
Dynamic Address Assigned Force Enable This field is used in slave mode of operation. |
WO
|
0x0
|
| 7 |
Reserved_7
|
Reserved bitfield added by Magillem |
WO
|
0x0
|
| 6 |
CCC_UPDATED_FORCE_EN
|
CCC Table Updated Force Enable This field is used in slave mode of operation. |
WO
|
0x0
|
| 5 |
TRANSFER_ABORT_FORCE_EN
|
Transfer Abort Force Enable This field is used in master mode of operation. |
WO
|
0x0
|
| 4 |
RESP_READY_FORCE_EN
|
Response Queue Ready Force Enable |
WO
|
0x0
|
| 3 |
CMD_QUEUE_READY_FORCE_EN
|
Command Queue Ready Force Enable |
WO
|
0x0
|
| 2 |
IBI_THLD_FORCE_EN
|
IBI Buffer Threshold Force Enable This field is used in master mode of operation. |
WO
|
0x0
|
| 1 |
RX_THLD_FORCE_EN
|
Receive Buffer Threshold Force Enable |
WO
|
0x0
|
| 0 |
TX_THLD_FORCE_EN
|
Transmit Buffer Threshold Force Enable |
WO
|
0x0
|