DVETASCR

         Trace Accumulate and Control Register


Module Instance	Base Address	Register Address
`i_ccu__DSU__1c000000__dve0`	`0x1C00E000`	`0x1C00E900`

Size: 32

Offset: 0x900

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Rsvd1` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Rsvd1` `RO 0x0`											`BufferRead` `RW 0x0`	`BufferClear` `RW 0x0`	`BufferIsCircular` `RW 0x0`	`BufferIsFull` `RO 0x0`	`BufferIsEmpty` `RO 0x1`

DVETASCR Fields


Bit	Name	Description	Access	Reset
31:5	`Rsvd1`	Reserved	`RO`	`0x0`
4	`BufferRead`	Write one to trigger a read	`RW`	`0x0`
3	`BufferClear`	Write 1 to clear the complete buffer	`RW`	`0x0`
2	`BufferIsCircular`	Enable circular buffer. 1: buffer drops older messages. 0: buffer drops newer messages.	`RW`	`0x0`
1	`BufferIsFull`	Set when the buffer is full	`RO`	`0x0`
0	`BufferIsEmpty`	Set when all entries in the buffer are read and the buffer is empty	`RO`	`0x1`