GICR3_MISCSTATUSR

         GICR3_MISCSTATUSR


Module Instance	Base Address	Register Address
`i_aps_gic__gic_axi4_slave__1d000000__GICRsgi3`	`0x1D0D0000`	`0x1D0DC000`

Size: 32

Offset: 0xC000

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`cpu_active` `RO 0x0`	`wake_request` `RO 0x0`	`RESERVED1` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RESERVED1` `RO 0x0`											`access_type` `RO 0x0`	`RESERVED0` `RO 0x0`	`EnableGrp1_s` `RO 0x0`	`EnableGrp1_ns` `RO 0x0`	`EnableGrp0` `RO 0x0`

GICR3_MISCSTATUSR Fields


Bit	Name	Description	Access	Reset
31	`cpu_active`	cpu_active	`RO`	`0x0`
30	`wake_request`	wake_request	`RO`	`0x0`
29:5	`RESERVED1`	RESERVED1	`RO`	`0x0`
4	`access_type`	access_type	`RO`	`0x0`
3	`RESERVED0`	RESERVED0	`RO`	`0x0`
2	`EnableGrp1_s`	EnableGrp1_s	`RO`	`0x0`
1	`EnableGrp1_ns`	EnableGrp1_ns	`RO`	`0x0`
0	`EnableGrp0`	EnableGrp0	`RO`	`0x0`