GICR0_IERRVR

         GICR0_IERRVR


Module Instance	Base Address	Register Address
`i_aps_gic__gic_axi4_slave__1d000000__GICRsgi0`	`0x1D070000`	`0x1D07C008`

Size: 32

Offset: 0xC008

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`valid_bit31` `RO 0x0`	`valid_bit30` `RO 0x0`	`valid_bit29` `RO 0x0`	`valid_bit28` `RO 0x0`	`valid_bit27` `RO 0x0`	`valid_bit26` `RO 0x0`	`valid_bit25` `RO 0x0`	`valid_bit24` `RO 0x0`	`valid_bit23` `RO 0x0`	`valid_bit22` `RO 0x0`	`valid_bit21` `RO 0x0`	`valid_bit20` `RO 0x0`	`valid_bit19` `RO 0x0`	`valid_bit18` `RO 0x0`	`valid_bit17` `RO 0x0`	`valid_bit16` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`valid_bit15` `RO 0x0`	`valid_bit14` `RO 0x0`	`valid_bit13` `RO 0x0`	`valid_bit12` `RO 0x0`	`valid_bit11` `RO 0x0`	`valid_bit10` `RO 0x0`	`valid_bit9` `RO 0x0`	`valid_bit8` `RO 0x0`	`valid_bit7` `RO 0x0`	`valid_bit6` `RO 0x0`	`valid_bit5` `RO 0x0`	`valid_bit4` `RO 0x0`	`valid_bit3` `RO 0x0`	`valid_bit2` `RO 0x0`	`valid_bit1` `RO 0x0`	`valid_bit0` `RO 0x0`

GICR0_IERRVR Fields


Bit	Name	Description	Access	Reset
31	`valid_bit31`	valid_bit31	`RO`	`0x0`
30	`valid_bit30`	valid_bit30	`RO`	`0x0`
29	`valid_bit29`	valid_bit29	`RO`	`0x0`
28	`valid_bit28`	valid_bit28	`RO`	`0x0`
27	`valid_bit27`	valid_bit27	`RO`	`0x0`
26	`valid_bit26`	valid_bit26	`RO`	`0x0`
25	`valid_bit25`	valid_bit25	`RO`	`0x0`
24	`valid_bit24`	valid_bit24	`RO`	`0x0`
23	`valid_bit23`	valid_bit23	`RO`	`0x0`
22	`valid_bit22`	valid_bit22	`RO`	`0x0`
21	`valid_bit21`	valid_bit21	`RO`	`0x0`
20	`valid_bit20`	valid_bit20	`RO`	`0x0`
19	`valid_bit19`	valid_bit19	`RO`	`0x0`
18	`valid_bit18`	valid_bit18	`RO`	`0x0`
17	`valid_bit17`	valid_bit17	`RO`	`0x0`
16	`valid_bit16`	valid_bit16	`RO`	`0x0`
15	`valid_bit15`	valid_bit15	`RO`	`0x0`
14	`valid_bit14`	valid_bit14	`RO`	`0x0`
13	`valid_bit13`	valid_bit13	`RO`	`0x0`
12	`valid_bit12`	valid_bit12	`RO`	`0x0`
11	`valid_bit11`	valid_bit11	`RO`	`0x0`
10	`valid_bit10`	valid_bit10	`RO`	`0x0`
9	`valid_bit9`	valid_bit9	`RO`	`0x0`
8	`valid_bit8`	valid_bit8	`RO`	`0x0`
7	`valid_bit7`	valid_bit7	`RO`	`0x0`
6	`valid_bit6`	valid_bit6	`RO`	`0x0`
5	`valid_bit5`	valid_bit5	`RO`	`0x0`
4	`valid_bit4`	valid_bit4	`RO`	`0x0`
3	`valid_bit3`	valid_bit3	`RO`	`0x0`
2	`valid_bit2`	valid_bit2	`RO`	`0x0`
1	`valid_bit1`	valid_bit1	`RO`	`0x0`
0	`valid_bit0`	valid_bit0	`RO`	`0x0`