GICR3_PWRR

         GICR3_PWRR


Module Instance	Base Address	Register Address
`i_aps_gic__gic_axi4_slave__1d000000__GICRlpi3`	`0x1D0C0000`	`0x1D0C0024`

Size: 32

Offset: 0x24

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RESERVED1` `RO 0x0`								`RDG` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RDG` `RO 0x0`	`RDGO` `RO 0x3`							`RESERVED0` `RO 0x0`				`RDGPO` `RO 0x1`	`RDGPD` `RW 0x1`	`RDAG` `WO 0x0`	`RDPD` `RW 0x1`

GICR3_PWRR Fields


Bit	Name	Description	Access	Reset
31:24	`RESERVED1`	RESERVED1	`RO`	`0x0`
23:15	`RDG`	RDG	`RO`	`0x0`
14:8	`RDGO`	RDGO	`RO`	`0x3`
7:4	`RESERVED0`	RESERVED0	`RO`	`0x0`
3	`RDGPO`	RDGPO	`RO`	`0x1`
2	`RDGPD`	RDGPD	`RW`	`0x1`
1	`RDAG`	RDAG	`WO`	`0x0`
0	`RDPD`	RDPD	`RW`	`0x1`