GICR2_CTLR

         GICR2_CTLR


Module Instance	Base Address	Register Address
`i_aps_gic__gic_axi4_slave__1d000000__GICRlpi2`	`0x1D0A0000`	`0x1D0A0000`

Size: 32

Offset: 0x

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`UWP` `RO 0x0`	`RESERVED2` `RW 0x0`				`DPG1S` `RW 0x0`	`DPG1NS` `RW 0x0`	`DPG0` `RW 0x0`	`RESERVED1` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RESERVED1` `RW 0x0`												`RWP` `RO 0x0`	`RESERVED0` `RW 0x0`		`EnableLPIs` `RW 0x0`

GICR2_CTLR Fields


Bit	Name	Description	Access	Reset
31	`UWP`	UWP	`RO`	`0x0`
30:27	`RESERVED2`	RESERVED2	`RW`	`0x0`
26	`DPG1S`	DPG1S	`RW`	`0x0`
25	`DPG1NS`	DPG1NS	`RW`	`0x0`
24	`DPG0`	DPG0	`RW`	`0x0`
23:4	`RESERVED1`	RESERVED1	`RW`	`0x0`
3	`RWP`	RWP	`RO`	`0x0`
2:1	`RESERVED0`	RESERVED0	`RW`	`0x0`
0	`EnableLPIs`	EnableLPIs	`RW`	`0x0`