HRS32

         HRS32 - FSM Monitor Register


Module Instance	Base Address	Register Address
`i_sdmmc__sdmmc_apb_slv__10808000____HRS____SEG_L4_MP_sdmmc_s_0x0_0x1000`	`0x10808000`	`0x10808080`

Size: 32

Offset: 0x80

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`LOAD` `RW 0x0`	`ADDR` `WO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`DATA` `RO 0x0`

HRS32 Fields

Bit Name Description Access Reset

Bit	Name	Description	Access	Reset
31	`LOAD`	LOAD - FSM monitor update request\n Setting this bit to 1 starts internal FSM monitor to load value from selected FSM.\n After finishing this bit will be automatically cleared by hardware and FSM status can be read.	`RW`	`0x0`
30:16	`ADDR`	ADDR - FSM address\n This field selects which FSM status will be read.\n All available status machines are listed in Debug section of User Guide.	`WO`	`0x0`
15:0	`DATA`	DATA - FSM status\n This register contains read FSM status. Before reading it user should select FSM address (ADDR), set LOAD bit and wait until hardware clears it.	`RO`	`0x0`

LOAD

              LOAD - FSM monitor update request\n
              Setting this bit to 1 starts internal FSM monitor to load value from selected FSM.\n
              After finishing this bit will be automatically cleared by hardware and FSM status can be read.

RW

0x0

30:16

ADDR

              ADDR - FSM address\n
              This field selects which FSM status will be read.\n
              All available status machines are listed in Debug section of User Guide.

WO

0x0

15:0

DATA

              DATA - FSM status\n
              This register contains read FSM status. Before reading it user should select FSM address (ADDR), set LOAD bit and wait until hardware clears it.

RO

0x0