HRS16 

         HRS16 - CMD/DAT output delay
Module Instance Base Address Register Address
i_sdmmc__sdmmc_apb_slv__10808000____HRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808000 0x10808040

Size: 32

Offset: 0x40

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

WRDATA1_SDCLK_DLY

RW 0x0

WRDATA0_SDCLK_DLY

RW 0x0

WRCMD1_SDCLK_DLY

RW 0x0

WRCMD0_SDCLK_DLY

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WRDATA1_DLY

RW 0x0

WRDATA0_DLY

RW 0x0

WRCMD1_DLY

RW 0x0

WRCMD0_DLY

RW 0x0

HRS16 Fields

Bit Name Description Access Reset
31:28 WRDATA1_SDCLK_DLY 
 Reserved
RW 0x0
27:24 WRDATA0_SDCLK_DLY 
              WRDATA0_SDCLK_DLY\n
              Value in this field defines a delay of the dfi_wrdata[7:0] signal. The delay is equal value * t_SDCLK/2.
RW 0x0
23:20 WRCMD1_SDCLK_DLY 
 Reserved
 RW 0x0
19:16 WRCMD0_SDCLK_DLY 
              WRCMD0_SDCLK_DLY\n
              Value in this field defines a delay of the dfi_wrcmd signal. The delay is equal value * t_SDCLK/2.
RW 0x0
15:12 WRDATA1_DLY 
Reserved
 RW 0x0
11:8 WRDATA0_DLY 
              WRDATA0_DLY\n
              Value in this field defines a delay of the dfi_wrdata[7:0] signal. The delay is equal value * t_SDMCLK.
RW 0x0
7:4 WRCMD1_DLY 
Reserved
 RW 0x0
3:0 WRCMD0_DLY 
              WRCMD0_DLY\n
              Value in this field defines a delay of the dfi_wrcmd[0] signal. The delay is equal value * t_SDMCLK.
RW 0x0