HRS09 

         HRS09 - PHY Control and Status Register
Module Instance Base Address Register Address
i_sdmmc__sdmmc_apb_slv__10808000____HRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808000 0x10808024

Size: 32

Offset: 0x24

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LVSI_CNT

RW 0xF

LVSI_TCKSEL

RW 0x7

Reserved_6

RO 0x0

RDDATA_EN

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RDCMD_EN

RW 0x0

Reserved_4

RO 0x0

EXTENDED_WR_MODE

RW 0x0

EXTENDED_RD_MODE

RW 0x0

PHY_INIT_COMPLETE

RO 0x0

PHY_SW_RESET

RW 0x1

HRS09 Fields

Bit Name Description Access Reset
31:28 LVSI_CNT 
              LVSI_CNT\n
              This field defines period of SDCLK pulse during LVS Identification. The period varies in range from LVSI_CNT * 2^(LVSI_TCKSEL+1) * t_CLK to (LVSI_CNT + 1) * 2^(LVSI_TCKSEL+1) * t_CLK.\n
              It is recommended to use lower LVSI_TCKSEL value and higher LVSI_CNT value to reduce SDCLK pulse period variation. The variation is +1/-1 LVSI_TCLKSEL unit.
RW 0xF
27:22 LVSI_TCKSEL 
              LVSI_TCKSEL\n
              This field defines unit for LVSI_CNT. [list] [*] 0 - 2*t_CLK (two CLK clock cycles) [*] 1 - 4*t_CLK (four CLK clock cycles) [*] 2 - 8*t_CLK (eight CLK clock cycles) [*] 3 - 16*t_CLK (sixteen clock cycles) [*] N - (2^(N+1))*t_CLK [/list]\n
              where N must equal 0 to 47. Values above 47 are reserved.
RW 0x7
21:17 Reserved_6 
Reserved bitfield added by Magillem
 RO 0x0
16 RDDATA_EN 
              RDDATA_EN\n
              If 1, dfi_rddata_en is forced to 1, else host logic controls the signal.
RW 0x0
15 RDCMD_EN 
              RDCMD_EN\n
              If 1, dfi_rdcmd_en is forced to 1, else host logic controls the signal.
RW 0x0
14:4 Reserved_4 
Reserved bitfield added by Magillem
 RO 0x0
3 EXTENDED_WR_MODE 
              EXTENDED_WR_MODE\n
              Controls sdphy_param_extended_wr_mode port.
              Non of software resets clear this register.
RW 0x0
2 EXTENDED_RD_MODE 
              EXTENDED_RD_MODE\n
              Controls sdphy_param_extended_rd_mode port.\n
              Non of software resets clear this register.
RW 0x0
1 PHY_INIT_COMPLETE 
              PHY_INIT_COMPLETE\n
              This field contains a value read from sdphy_dfi_init_complete port.
RO 0x0
0 PHY_SW_RESET 
              PHY_SW_RESET\n
              This field controls sdphy_dll_rst_n.
RW 0x1