HRS05


Module Instance	Base Address	Register Address
`i_sdmmc__sdmmc_apb_slv__10808000____HRS____SEG_L4_MP_sdmmc_s_0x0_0x1000`	`0x10808000`	`0x10808014`

Size: 32

Offset: 0x14

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`PHYREGDATA` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`PHYREGDATA` `RW 0x0`

HRS05 Fields

Bit Name Description Access Reset

31:0

Bit	Name	Description	Access	Reset
31:0	`PHYREGDATA`	PHYREGDATA - PHY Register Data Port\n Access to this register generates read or write transaction to Combo PHY Register.\n When this field is read, a read transaction is sent to PHY through APB interface. Value received in the transaction is passed back as the access result.\n When this field is write, a write transaction is sent to PHY through APB interface along with the written data.\n Host Controller -- Combo PHY APB interface does not support unaligned transfers, and so access to this field is limited to 32-bit transactions only. Unaligned (16-bit or 8-bit) access to this field may lead to unexpected result.	`RW`	`0x0`

PHYREGDATA

              PHYREGDATA - PHY Register Data Port\n
              Access to this register generates read or write transaction to Combo PHY Register.\n
              When this field is read, a read transaction is sent to PHY through APB interface. Value received in the transaction is passed back as the access result.\n
              When this field is write, a write transaction is sent to PHY through APB interface along with the written data.\n
              Host Controller -- Combo PHY APB interface does not support unaligned transfers, and so access to this field is limited to 32-bit transactions only. Unaligned (16-bit or 8-bit) access to this field may lead to unexpected result.

RW

0x0