HRS03 

         
            HRS03 - AXI ERROR Responses Register\n
            These registers extend the standard set of SD-HOST interrupt statuses by information about AXI interface exceptions.\n
            The registers are divided into three groups:\n
            - Signal Enable registers allow to enable/mask signaling the Interrupt Status registers (HRS03[3:0]) on interrupt port\n
            - Status Enable registers allow to enable/disable interrupt source for each Interrupt Status separately\n
            - Interrupt Status are triggered whenever the interrupt source is detected and the Status Enable register is enabled\n
Module Instance Base Address Register Address
i_sdmmc__sdmmc_apb_slv__10808000____HRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808000 0x1080800C

Size: 32

Offset: 0xC

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_12

RO 0x0

AER_IEBS

RW 0x0

AER_IEBD

RW 0x0

AER_IERS

RW 0x0

AER_IERD

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_8

RO 0x0

AER_SENBS

RW 0x0

AER_SENBD

RW 0x0

AER_SENRS

RW 0x0

AER_SENRD

RW 0x0

Reserved_4

RO 0x0

AER_BS

RW 0x0

AER_BD

RW 0x0

AER_RS

RW 0x0

AER_RD

RW 0x0

HRS03 Fields

Bit Name Description Access Reset
31:20 Reserved_12 
Reserved bitfield added by Magillem
 RO 0x0
19 AER_IEBS 
              AER_IEBS - Signal Enable for AXI ERROR Response B channel: SLVERR\n
              1 - interrupt enable\n
              0 - interrupt masked
RW 0x0
18 AER_IEBD 
              AER_IEBD - Signal Enable for AXI ERROR Response B channel: DECERR\n
              1 - interrupt enable\n
              0 - interrupt masked
RW 0x0
17 AER_IERS 
              AER_IERS - Signal Enable for AXI ERROR Response R channel: SLVERR\n
              1 - interrupt enable\n
              0 - interrupt masked
RW 0x0
16 AER_IERD 
              AER_IERD - Signal Enable for AXI ERROR Response R channel: DECERR\n
              1 - interrupt enable\n
              0 - interrupt masked
RW 0x0
15:12 Reserved_8 
Reserved bitfield added by Magillem
 RO 0x0
11 AER_SENBS 
              AER_SENBS - Status Enable for AXI ERROR Response B channel: SLVERR\n
              1 - status enable\n
              0 - status disable
RW 0x0
10 AER_SENBD 
              AER_SENBD - Status Enable for AXI ERROR Response B channel: DECERR\n
              1 - status enable\n
              0 - status disable
RW 0x0
9 AER_SENRS 
              AER_SENRS - Status Enable for AXI ERROR Response R channel: SLVERR\n
              1 - status enable\n
              0 - status disable
RW 0x0
8 AER_SENRD 
              AER_SENRD - Status Enable for AXI ERROR Response R channel: DECERR\n
              1 - status enable\n
              0 - status disable
RW 0x0
7:4 Reserved_4 
Reserved bitfield added by Magillem
 RO 0x0
3 AER_BS 
              AER_BS - AXI ERROR Response B channel: SLVERR\n
              This bit is set when a SLVERR is detected on AXI Master bus in B channel (Write Response Channel).
RW 0x0
2 AER_BD 
              AER_BD - AXI ERROR Response B channel: DECERR\n
              This bit is set when a DECERR is detected on AXI Master bus in B channel (Write Response Channel).
RW 0x0
1 AER_RS 
              AER_RS - AXI ERROR Response R channel: SLVERR\n
              This bit is set when a SLVERR is detected on AXI Master bus in R channel (READ Response Channel).
RW 0x0
0 AER_RD 
              AER_RD - AXI ERROR Response R channel: DECERR\n
              This bit is set when a DECERR is detected on AXI Master bus in R channel (READ Response Channel).
RW 0x0