HRS01

         HRS01 - Debounce Setting Register


Module Instance	Base Address	Register Address
`i_sdmmc__sdmmc_apb_slv__10808000____HRS____SEG_L4_MP_sdmmc_s_0x0_0x1000`	`0x10808000`	`0x10808004`

Size: 32

Offset: 0x4

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_1` `RO 0x0`								`DP` `RW 0x32`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`DP` `RW 0x32`

HRS01 Fields

Bit Name Description Access Reset

31:24

Bit	Name	Description	Access	Reset
31:24	`Reserved_1`	Reserved bitfield added by Magillem	`RO`	`0x0`
23:0	`DP`	DP - Debounce Period\n Defines the number of system (clk) clock cycles used by the debounce logic, which detects card insertion and removal events. The debounce period is equal to DP * tclk, where tclk is the period of clk clock. If there is no change on pad_mem_ctrl_0 signal level for a programmed debounce period, the core logic decodes the card state as stable and triggers card_inserted or card_removed event. Typically, DP value should be chosen to obtain the period of 20ms.\n This register is reset to DEBOUNCE_PERIOD.	`RW`	`0x32`

Reserved_1

Reserved bitfield added by Magillem

RO

0x0

23:0

DP

              DP - Debounce Period\n
              Defines the number of system (clk) clock cycles used by the debounce logic, which detects card insertion and removal events. The debounce period is equal to DP * tclk, where tclk is the period of clk clock. If there is no change on pad_mem_ctrl_0 signal level for a programmed debounce period, the core logic decodes the card state as stable and triggers card_inserted or card_removed event. Typically, DP value should be chosen to obtain the period of 20ms.\n
              This register is reset to DEBOUNCE_PERIOD.

RW

0x32