GITS0_FCTLR

         GITS0_FCTLR


Module Instance	Base Address	Register Address
`i_aps_gic__gic_axi4_slave__1d000000__GITS0`	`0x1D040000`	`0x1D040020`

Size: 32

Offset: 0x20

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`DCC` `RW 0x0`	`PWE` `RW 0x0`	`RESERVED2` `RO 0x0`											`IEC` `RW 0x0`	`IDC` `RW 0x0`	`ICC` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RESERVED1` `RO 0x0`				`DMA` `RW 0x0`	`RESERVED0` `RO 0x0`	`QD` `RW 0x0`	`AEE` `RW 0x0`	`CGO` `RW 0x0`				`CEE` `RW 0x0`	`UEE` `RW 0x0`	`LTE` `RW 0x0`	`SIP` `RW 0x0`

GITS0_FCTLR Fields


Bit	Name	Description	Access	Reset
31	`DCC`	DCC	`RW`	`0x0`
30	`PWE`	PWE	`RW`	`0x0`
29:19	`RESERVED2`	RESERVED2	`RO`	`0x0`
18	`IEC`	IEC	`RW`	`0x0`
17	`IDC`	IDC	`RW`	`0x0`
16	`ICC`	ICC	`RW`	`0x0`
15:12	`RESERVED1`	RESERVED1	`RO`	`0x0`
11	`DMA`	DMA	`RW`	`0x0`
10	`RESERVED0`	RESERVED0	`RO`	`0x0`
9	`QD`	QD	`RW`	`0x0`
8	`AEE`	AEE	`RW`	`0x0`
7:4	`CGO`	CGO	`RW`	`0x0`
3	`CEE`	CEE	`RW`	`0x0`
2	`UEE`	UEE	`RW`	`0x0`
1	`LTE`	LTE	`RW`	`0x0`
0	`SIP`	SIP	`RW`	`0x0`