GITS0_CFGID

         GITS0_CFGID


Module Instance	Base Address	Register Address
`i_aps_gic__gic_axi4_slave__1d000000__GITS0`	`0x1D040000`	`0x1D04F000`

Size: 32

Offset: 0xF000

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Event_Cache_Index_Bits` `RO 0x7`				`Device_Cache_Index_Bits` `RO 0x4`				`Collection_Cache_Index_Bits` `RO 0x3`				`RESERVED0` `RO 0x0`	`Cache_ECC` `RO 0x1`	`Low_Latency_Support` `RO 0x1`	`MSI_64` `RO 0x1`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Target_Bits` `RO 0x2`				`LPI_Credit_Count` `RO 0x0`				`ITS_NUMBER` `RO 0x0`

GITS0_CFGID Fields


Bit	Name	Description	Access	Reset
31:28	`Event_Cache_Index_Bits`	Event_Cache_Index_Bits	`RO`	`0x7`
27:24	`Device_Cache_Index_Bits`	Device_Cache_Index_Bits	`RO`	`0x4`
23:20	`Collection_Cache_Index_Bits`	Collection_Cache_Index_Bits	`RO`	`0x3`
19	`RESERVED0`	RESERVED0	`RO`	`0x0`
18	`Cache_ECC`	Cache_ECC	`RO`	`0x1`
17	`Low_Latency_Support`	Low_Latency_Support	`RO`	`0x1`
16	`MSI_64`	MSI_64	`RO`	`0x1`
15:12	`Target_Bits`	Target_Bits	`RO`	`0x2`
11:8	`LPI_Credit_Count`	LPI_Credit_Count	`RO`	`0x0`
7:0	`ITS_NUMBER`	ITS_NUMBER	`RO`	`0x0`