GICD_ICLAR10

         GICD_ICLAR10


Module Instance	Base Address	Register Address
`i_aps_gic__gic_axi4_slave__1d000000__GICD`	`0x1D000000`	`0x1D00E028`

Size: 32

Offset: 0xE028

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`classes15` `RW 0x0`		`classes14` `RW 0x0`		`classes13` `RW 0x0`		`classes12` `RW 0x0`		`classes11` `RW 0x0`		`classes10` `RW 0x0`		`classes9` `RW 0x0`		`classes8` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`classes7` `RW 0x0`		`classes6` `RW 0x0`		`classes5` `RW 0x0`		`classes4` `RW 0x0`		`classes3` `RW 0x0`		`classes2` `RW 0x0`		`classes1` `RW 0x0`		`classes0` `RW 0x0`

GICD_ICLAR10 Fields


Bit	Name	Description	Access	Reset
31:30	`classes15`	classes15	`RW`	`0x0`
29:28	`classes14`	classes14	`RW`	`0x0`
27:26	`classes13`	classes13	`RW`	`0x0`
25:24	`classes12`	classes12	`RW`	`0x0`
23:22	`classes11`	classes11	`RW`	`0x0`
21:20	`classes10`	classes10	`RW`	`0x0`
19:18	`classes9`	classes9	`RW`	`0x0`
17:16	`classes8`	classes8	`RW`	`0x0`
15:14	`classes7`	classes7	`RW`	`0x0`
13:12	`classes6`	classes6	`RW`	`0x0`
11:10	`classes5`	classes5	`RW`	`0x0`
9:8	`classes4`	classes4	`RW`	`0x0`
7:6	`classes3`	classes3	`RW`	`0x0`
5:4	`classes2`	classes2	`RW`	`0x0`
3:2	`classes1`	classes1	`RW`	`0x0`
1:0	`classes0`	classes0	`RW`	`0x0`