GICD_CFGID

         GICD_CFGID


Module Instance	Base Address	Register Address
`i_aps_gic__gic_axi4_slave__1d000000__GICD`	`0x1D000000`	`0x1D00F000`

Size: 64

Offset: 0xF000

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
`RESERVED3` `RO 0x0`											`PEwidth` `RO 0x0`
47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
`Affinity3Bits` `RO 0x0`				`Affinity2Bits` `RO 0x0`				`Affinity1Bits` `RO 0x0`				`Affinity0Bits` `RO 0x0`
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RESERVED2` `RO 0x0`											`SPIGroups` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`SPIGroups` `RO 0x0`	`ChipAffinityLevel` `RO 0x0`	`DirectLPI` `RO 0x0`	`LPISupport` `RO 0x0`	`RESERVED1` `RO 0x0`				`SocketNumber` `RO 0x0`				`RESERVED0` `RO 0x0`			`SocketOffline` `RO 0x0`

GICD_CFGID Fields


Bit	Name	Description	Access	Reset
63:53	`RESERVED3`	RESERVED3	`RO`	`0x0`
52:48	`PEwidth`	PEwidth	`RO`	`0x0`
47:44	`Affinity3Bits`	Affinity3Bits	`RO`	`0x0`
43:40	`Affinity2Bits`	Affinity2Bits	`RO`	`0x0`
39:36	`Affinity1Bits`	Affinity1Bits	`RO`	`0x0`
35:32	`Affinity0Bits`	Affinity0Bits	`RO`	`0x0`
31:21	`RESERVED2`	RESERVED2	`RO`	`0x0`
20:15	`SPIGroups`	SPIGroups	`RO`	`0x0`
14	`ChipAffinityLevel`	ChipAffinityLevel	`RO`	`0x0`
13	`DirectLPI`	DirectLPI	`RO`	`0x0`
12	`LPISupport`	LPISupport	`RO`	`0x0`
11:8	`RESERVED1`	RESERVED1	`RO`	`0x0`
7:4	`SocketNumber`	SocketNumber	`RO`	`0x0`
3:1	`RESERVED0`	RESERVED0	`RO`	`0x0`
0	`SocketOffline`	SocketOffline	`RO`	`0x0`