XAIUTCR 

         Transaction Control Register
Module Instance Base Address Register Address
i_ccu__DSU__1c000000__FPGA2SOC 0x1C001000 0x1C001040

Size: 32

Offset: 0x40

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Rsvd4

RO 0x0

TransOrderModeWr

RW 0x2

TransOrderModeRd

RW 0x2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Rsvd3

RO 0x0

SysCoAttach

RW 0x0

SysCoDisable

RW 0x0

Rsvd2

RO 0x0

EventDisable

RW 0x0

Rsvd1

RO 0x0

XAIUTCR Fields

Bit Name Description Access Reset
31:20 Rsvd4 
Reserved
 RO 0x0
19:18 TransOrderModeWr 
This setting controls transaction ordering based on AXI ID 
            0x0: Reserved 
            0x1: Resreved 
            0x2: PCIe ordering rules 
            0x3: Strict request ordering mode
 RW 0x2
17:16 TransOrderModeRd 
This setting controls transaction ordering based on AXI ID 
            0x0: Reserved 
            0x1: Reserved 
            0x2: PCIe ordering rules 
            0x3: Strict request ordering mode
 RW 0x2
15:10 Rsvd3 
Reserved
 RO 0x0
9 SysCoAttach 
Writing 1 to this bit when the status register bit SysCoAttached is 0 starts an attach sequence. Writing 0 to this bit when the status register bit SysCoAttached is 1 starts a detach sequence.
 RW 0x0
8 SysCoDisable 
Setting this disables SysCo.
 RW 0x0
7:5 Rsvd2 
Reserved
 RO 0x0
4 EventDisable 
Setting this disables Event handling.
 RW 0x0
3:0 Rsvd1 
Reserved
 RO 0x0