LLPBMTXTIM 

         LPBM TX TIMER REGISTER
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_link__SEG_L4_AHB_USB1_0x0_0x100000 0x1100D000 0x1100D044

Size: 32

Offset: 0x44

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_2

RO 0x0

lfps_lpbs_tpwm_clk

RW 0x113

Reserved_1

RW 0x0

lfps_lbps_burst1_clk

RW 0xC8

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

lfps_lbps_burst1_clk

RW 0xC8

lfps_lbps_burst0_clk

RW 0x50

LLPBMTXTIM Fields

Bit Name Description Access Reset
31:30 Reserved_2 
Reserved
 RO 0x0
29:20 lfps_lpbs_tpwm_clk 
LFPS LBPS TPWM CLKS
   - This field is encoded as the Gen1 link_clk (8ns) count.
   -- 1: 8ns
   -- 2: 16ns
   -- 3: 24ns, and so on
 RW 0x113
19:18 Reserved_1 
Reserved
 RW 0x0
17:8 lfps_lbps_burst1_clk 
LFPS LBPS BURST1 CLKs
   - This field is encoded as the Gen1 link_clk (8ns) count.
   -- 1: 8ns
   -- 2: 16ns
   -- 3: 24ns, and so on
 RW 0xC8
7:0 lfps_lbps_burst0_clk 
LFPS LBPS BURST0 CLKs
   - This field is encoded as the Gen1 link_clk (8ns) count.
   -- 1: 8ns
   -- 2: 16ns
   -- 3: 24ns, and so on
 RW 0x50