GUCTL4
Global User Control Register 4
Module Instance | Base Address | Register Address |
---|---|---|
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_gbl__SEG_L4_AHB_USB1_0x0_0x100000
|
0x1100C100
|
0x1100C634
|
Size: 32
Offset: 0x534
Access: RW
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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GUCTL4 Fields
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
31 |
reserved_31
|
Reserved |
RO
|
0x0
|
30:26 |
SSP_BWD_OVHD_ADJ
|
SS/SSP bandwidth adjuest control GUCTL4[30]=1 indicates GUCTL4[29:26] will be subtracted from the overhead for each uframe(125us) GUCTL4[30]=0 indicates GUCTL4[29:26] will be added the overhead for each uframe(125us) GUCTL4[29:26] indicates duration in terms of 1us. |
RW
|
0x0
|
25:21 |
reserved_25_21
|
Reserved |
RO
|
0x0
|
20:19 |
LOA_EOP_CHECK_CLKS_WORD
|
Number of clock cycles to check for EOP SE0 for LOA logic Note: - This field only affects USB2.0 FS operation in UTMI 16bit mode. The U2 root hub logic checks for the programmed number of clocks of SE0 to validate an EOP for a packet. - The actual number of clocks checked will be the value programmed plus 1. So a value 1 will results is checking for 2 clocks of SE0. Value of 3 will do 4 clocks of SE0 check and so on. - The default value is 1, which results in 2 clocks of SE0 check. |
RW
|
0x0
|
18:17 |
LOA_EOP_CHECK_CLKS_BYTE
|
Number of clock cycles to check for EOP SE0 for LOA logic Note: - This field only affects USB2.0 FS operation in UTMI 8bit mode. The U2 root hub logic checks for the programmed number of clocks of SE0 to validate an EOP for a packet. - The actual number of clocks checked will be the value programmed plus 1. So a value 1 will results is checking for 2 clocks of SE0. Value of 3 will do 4 clocks of SE0 check and so on. - The default value is 1, which results in 2 clocks of SE0 check. |
RW
|
0x0
|
16:0 |
CSR_TIMEOUT_VL
|
CSR Timeout Value This register field determines the CSR access timeout value. Note: - It is not recommended to change this register field value except for simulation and debug purpose. - Bit-bash testing is not recommended for this register field due to side-effects of early timeout access with ram_clk/link_clk domain registers. |
RW
|
0x1FFFF
|