GFLADJ 

         Global Frame Length Adjustment Register
  This register provides options for the software to control the controller behavior with respect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It provides an option to override the fladj_30mhz_reg sideband signal. This also facilitates hardware LPM in host mode with the SOF or ITP counters being run from the ref_clk signal.
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_gbl__SEG_L4_AHB_USB1_0x0_0x100000 0x1100C100 0x1100C630

Size: 32

Offset: 0x530

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GFLADJ_REFCLK_240MHZDECR_PLS1

RW 0x0

GFLADJ_REFCLK_240MHZ_DECR

RW 0xC

GFLADJ_REFCLK_LPM_SEL

RW 0x1

reserved_22

RW 0x0

GFLADJ_REFCLK_FLADJ

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GFLADJ_REFCLK_FLADJ

RW 0x0

GFLADJ_30MHZ_SDBND_SEL

RW 0x0

reserved_6

RW 0x0

GFLADJ_30MHZ

RW 0x20

GFLADJ Fields

Bit Name Description Access Reset
31 GFLADJ_REFCLK_240MHZDECR_PLS1 
GFLADJ_REFCLK_240MHZDECR_PLS1
  
  This field indicates that the decrement value that the controller applies for each ref_clk  must be GFLADJ_REFCLK_240MHZ_DECR and GFLADJ_REFCLK_240MHZ_DECR +1 alternatively on each ref_clk.
  
  Set this bit to a '1' only if the fractional component of 240/ref_frequency is greater than or equal to 0.5. 
  
  Examples:
  
  If the ref_clk is 19.2 MHz then
   - GUCTL.REF_CLK_PERIOD = 52
   - GFLADJ.GFLADJ_REFCLK_240MHZ_DECR = (240/19.2) = 12.5
   - GFLADJ.GFLADJ_REFCLK_240MHZDECR_PLS1 = 1
  If the ref_clk is 24 MHz then
   - GUCTL.REF_CLK_PERIOD = 41
   - GFLADJ.GFLADJ_REFCLK_240MHZ_DECR = (240/24) = 10
   - GFLADJ.GFLADJ_REFCLK_240MHZDECR_PLS1 = 0
 RW 0x0
30:24 GFLADJ_REFCLK_240MHZ_DECR 
This field indicates the decrement value that the controller applies for each ref_clk in order to derive a frame timer in terms of a 240-MHz clock. 
  
  The value is derived as follows:
  
  GFLADJ_REFCLK_240MHZ_DECR = 240/ref_clk_frequency
  
  Examples:
  If the ref_clk is 24 MHz then
   - GUCTL.REF_CLK_PERIOD = 41
   - GFLADJ.GFLADJ_REFCLK_240MHZ_DECR = 240/24 = 10
  If the ref_clk is 17 MHz then
   - GUCTL.REF_CLK_PERIOD = 58
   - GFLADJ.GFLADJ_REFCLK_240MHZ_DECR = 240/17 = 14
 RW 0xC
23 GFLADJ_REFCLK_LPM_SEL 
The ref_clk frequencies supported are 16/17/19.2/20/24/39.7 MHz. 
   - Host mode: This bit internally enables the functionality of running SOF/ITP counters on the ref_clk.
   - Device mode with DWC_USB31_LPM_SUSP_OFF = 1: This bit internally enables the functionality of running SOF counters on the ref_clk in 2.0 speeds.
RW 0x1
22 reserved_22 
Reserved_22
 RW 0x0
21:8 GFLADJ_REFCLK_FLADJ 
This field indicates the frame length adjustment to be applied to the SOF/ITP counter that is running on the ref_clk. 
  
  This register value is used to adjust the SOF and ITP interval.
  
  The value is derived as follows:
  
  FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_period)) * ref_clk_period
  where
   - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the decimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field.
   - the ref_clk_period is the ref_clk period including the fractional value.
  Example:
  If the ref_clk is 24 MHz then
   - GUCTL.REF_CLK_PERIOD = 41
   - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value)
RW 0x0
7 GFLADJ_30MHZ_SDBND_SEL 
GFLADJ_30MHZ_SDBND_SEL
  
  This field selects whether to use the input signal fladj_30mhz_reg or the GFLADJ.GFLADJ_30MHZ to adjust the frame length for the SOF/ITP.
  When this bit is set to,
   - 1, the controller uses the register field GFLADJ.GFLADJ_30MHZ value
   - 0, the controller uses the input signal fladj_30mhz_reg value
 RW 0x0
6 reserved_6 
Reserved_6
 RW 0x0
5:0 GFLADJ_30MHZ 
GFLADJ_30MHZ
  
  This field indicates the value that is used for frame length adjustment instead of considering from the sideband input signal fladj_30mhz_reg. 
  
  This enables post-silicon frame length adjustment in case the input signal fladj_30mhz_reg is connected to a wrong value or is not valid. 
  
  For details on how to set this value, refer to section 5.2.4, "Frame Length Adjustment Register (FLADJ)," of the  xHCI Specification.
 RW 0x20