DMAC_RESETREG

         This register is used to initiate the Software Reset to DW_axi_dmac.


Module Instance	Base Address	Register Address
`i_dma__dmac1_ahb_slv__10dc0000__Common_Registers_Address_Block__SEG_L4_AHB_dmac1_s_0x0_0x10000`	`0x10DC0000`	`0x10DC0058`

Size: 64

Offset: 0x58

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
`RSVD_DMAC_ResetReg_1to63` `RO 0x0`
47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
`RSVD_DMAC_ResetReg_1to63` `RO 0x0`
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RSVD_DMAC_ResetReg_1to63` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RSVD_DMAC_ResetReg_1to63` `RO 0x0`															`DMAC_RST` `RW 0x0`

DMAC_RESETREG Fields

Bit Name Description Access Reset

63:1

Bit	Name	Description	Access	Reset
63:1	`RSVD_DMAC_ResetReg_1to63`	DMAC_ResetReg (bits 1to63) Reserved bits - Read Only	`RO`	`0x0`
0	`DMAC_RST`	DMAC Reset Request bit Software writes 1 to this bit to reset the DW_axi_dmac and polls this bit to see it as 0. DW_axi_dmac resets all the modules except the slave bus interface module and clears this bit to 0. NOTE: Software is not allowed to write 0 to this bit.	`RW`	`0x0`

RSVD_DMAC_ResetReg_1to63

DMAC_ResetReg (bits 1to63) Reserved bits - Read Only

RO

0x0

DMAC_RST

DMAC Reset Request bit
Software writes 1 to this bit to reset the DW_axi_dmac and polls this bit to see it as 0. DW_axi_dmac resets all the modules
except the slave bus interface module and clears this bit to 0.
NOTE: Software is not allowed to write 0 to this bit.

RW

0x0