CH3_INTSIGNAL_ENABLEREG 

         This register contains fields that are used to enable the generation of port level interrupt at the channel level.
Module Instance Base Address Register Address
i_dma__dmac0_ahb_slv__10db0000__Channel3_Registers_Address_Block__SEG_L4_AHB_dmac0_s_0x0_0x10000 0x10DB0300 0x10DB0390

Size: 64

Offset: 0x90

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_36to63

RO 0x0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_36to63

RO 0x0

Enable_ECC_PROT_UIDMem_UnCorrERR_IntSignal

RO 0x0

Enable_ECC_PROT_UIDMem_CorrERR_IntSignal

RO 0x0

Enable_ECC_PROT_CHMem_UnCorrERR_IntSignal

RO 0x0

Enable_ECC_PROT_CHMem_CorrERR_IntSignal

RO 0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Enable_CH_ABORTED_IntSignal

RW 0x0

Enable_CH_DISABLED_IntSignal

RW 0x0

Enable_CH_SUSPENDED_IntSignal

RW 0x0

Enable_CH_SRC_SUSPENDED_IntSignal

RW 0x0

Enable_CH_LOCK_CLEARED_IntSignal

RW 0x0

RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_26

RO 0x0

Enable_SLVIF_WRPARITY_ERR_IntSignal

RO 0x0

RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_22to24

RO 0x0

Enable_SLVIF_WRONHOLD_ERR_IntSignal

RW 0x0

Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntSignal

RW 0x0

Enable_SLVIF_WRONCHEN_ERR_IntSignal

RW 0x0

Enable_SLVIF_RD2RWO_ERR_IntSignal

RW 0x0

Enable_SLVIF_WR2RO_ERR_IntSignal

RW 0x0

Enable_SLVIF_DEC_ERR_IntSignal

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15

RO 0x0

Enable_SLVIF_MULTIBLKTYPE_ERR_IntSignal

RW 0x0

Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntSignal

RW 0x0

Enable_LLI_WR_SLV_ERR_IntSignal

RW 0x0

Enable_LLI_RD_SLV_ERR_IntSignal

RW 0x0

Enable_LLI_WR_DEC_ERR_IntSignal

RW 0x0

Enable_LLI_RD_DEC_ERR_IntSignal

RW 0x0

Enable_DST_SLV_ERR_IntSignal

RW 0x0

Enable_SRC_SLV_ERR_IntSignal

RW 0x0

Enable_DST_DEC_ERR_IntSignal

RW 0x0

Enable_SRC_DEC_ERR_IntSignal

RW 0x0

Enable_DST_TRANSCOMP_IntSignal

RW 0x0

Enable_SRC_TRANSCOMP_IntSignal

RW 0x0

RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2

RO 0x0

Enable_DMA_TFR_DONE_IntSignal

RW 0x0

Enable_BLOCK_TFR_DONE_IntSignal

RW 0x0

CH3_INTSIGNAL_ENABLEREG Fields

Bit Name Description Access Reset
63:36 RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_36to63 
DMAC Channelx Interrupt Signal Enable Register (bits 36to63) Reserved bits - Read Only
 RO 0x0
35 Enable_ECC_PROT_UIDMem_UnCorrERR_IntSignal 
Channel x Unique ID Memory Interface ECC Protection Uncorrectable Error Interrupt Signal enable.
 - 0: Disable the propagation of Channel x UID Memory Interface Uncorrectable Error to generate a port level interrupt.
 - 1: Enable the propagation of Channel x UID Memory Interface Uncorrectable Error to generate a port level interrupt.
Value Description
0x0 Disable the propagation of UID Memory ECC Uncorrectable error Interrupt to port level interrupt
0x1 Enable the propagation of UID Memory ECC Uncorrectable error Interrupt to port level interrupt
RO 0x0
34 Enable_ECC_PROT_UIDMem_CorrERR_IntSignal 
Channel x Unique ID Memory Interface ECC Protection Correctable Error Interrupt Signal enable.
 - 0: Disable the propagation of Channel x UID Memory Interface Correctable Error to generate a port level interrupt.
 - 1: Enable the propagation of Channel x UID Memory Interface Correctable Error to generate a port level interrupt.
Value Description
0x0 Disable the propagation of UID Memory ECC Correctable error Interrupt to port level interrupt
0x1 Enable the propagation of UID Memory ECC Correctable error Interrupt to port level interrupt
RO 0x0
33 Enable_ECC_PROT_CHMem_UnCorrERR_IntSignal 
Channel x Channel Memory Interface ECC Protection Uncorrectable Error Interrupt Signal enable.
 - 0: Disable the propagation of Channel x Channel Memory Interface Uncorrectable Error to generate a port level interrupt.
 - 1: Enable the propagation of Channel x Channel Memory Interface Uncorrectable Error to generate a port level interrupt.
Value Description
0x0 Disable the propagation of Channel Memory ECC Uncorrectable error Interrupt to port level interrupt
0x1 Enable the propagation of Channel Memory ECC Uncorrectable error Interrupt to port level interrupt
RO 0x0
32 Enable_ECC_PROT_CHMem_CorrERR_IntSignal 
Channel x Channel Memory Interface ECC Protection Correctable Error Interrupt Signal enable.
 - 0: Disable the propagation of Channel x Channel Memory Interface Correctable Error to generate a port level interrupt.
 - 1: Enable the propagation of Channel x Channel Memory Interface Correctable Error to generate a port level interrupt.
Value Description
0x0 Disable the propagation of Channel Memory ECC Correctable error Interrupt to port level interrupt
0x1 Enable the propagation of Channel Memory ECC Correctable error Interrupt to port level interrupt
RO 0x0
31 Enable_CH_ABORTED_IntSignal 
Channel Aborted Signal Enable.
 - 0: Disable the propagation of Channel Aborted Interrupt to generate a port level interrupt
 - 1: Enable the propagation of Channel Aborted Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of Channel Aborted Interrupt to generate a port level interrupt
0x1 Enable the propagation of Channel Aborted Interrupt to generate a port level interrupt
RW 0x0
30 Enable_CH_DISABLED_IntSignal 
Channel Disabled Signal Enable.
 - 0: Disable the propagation of Channel Disabled Interrupt to generate a port level interrupt
 - 1: Enable the propagation of Channel Disabled Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of Channel Disabled Interrupt to generate a port level interrupt
0x1 Enable the propagation of Channel Disabled Interrupt to generate a port level interrupt
RW 0x0
29 Enable_CH_SUSPENDED_IntSignal 
Channel Suspended Signal Enable.
 - 0: Disable the propagation of Channel Suspended Interrupt to generate a port level interrupt
 - 1: Enable the propagation of Channel Suspended Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of Channel Suspended Interrupt to generate a port level interrupt
0x1 Enable the propagation of Channel Suspended Interrupt to generate a port level interrupt
RW 0x0
28 Enable_CH_SRC_SUSPENDED_IntSignal 
Channel Source Suspended Signal Enable.
 - 0: Disable the propagation of Channel Source Suspended Interrupt to generate a port level interrupt
 - 1: Enable the propagation of Channel Source Suspended Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of Channel Source Suspended Interrupt to generate a port level interrupt
0x1 Enable the propagation of Channel Source Suspended Interrupt to generate a port level interrupt
RW 0x0
27 Enable_CH_LOCK_CLEARED_IntSignal 
Channel Lock Cleared Signal Enable.
 - 0: Disable the propagation of Channel Lock Cleared Interrupt to generate a port level interrupt
 - 1: Enable the propagation of Channel Lock Cleared Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of Channel Lock Cleared Interrupt to generate a port level interrupt
0x1 Enable the propagation of Channel Lock Cleared Interrupt to generate a port level interrupt
RW 0x0
26 RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_26 
DMAC Channelx Interrupt Signal Enable Register (bit 26) Reserved bit - Read Only
 RO 0x0
25 Enable_SLVIF_WRPARITY_ERR_IntSignal 
Slave Interface Write Parity Error Signal Enable.
 - 0: Disable the propagation of Slave Interface Write Parity Error Interrupt to generate a port level interrupt
 - 1: Enable the propagation of Slave Interface Write Parity Error Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of Slave Interface Write Parity Error Interrupt to generate a port level interrupt
0x1 Enable the propagation of Slave Interface Write Parity Error Interrupt to generate a port level interrupt
RO 0x0
24:22 RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_22to24 
DMAC Channelx Interrupt Signal Enable Register (bits 22to24) Reserved bits - Read Only
 RO 0x0
21 Enable_SLVIF_WRONHOLD_ERR_IntSignal 
Slave Interface Write On Hold Error Signal Enable.
 - 0: Disable the propagation of Slave Interface Write On Hold Error Interrupt to generate a port level interrupt
 - 1: Enable the propagation of Slave Interface Write On Hold Error Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of Slave Interface Write On Hold Error Interrupt to generate a port level interrupt
0x1 Enable the propagation of Slave Interface Write On Hold Error Interrupt to generate a port level interrupt
RW 0x0
20 Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntSignal 
Shadow Register Write On Valid Error Signal Enable.
 - 0: Disable the propagation of Shadow Register Write On Valid Error Interrupt to generate a port level interrupt
 - 1: Enable the propagation of Shadow register Write On Valid Error Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of Shadow Register Write On Valid Error Interrupt to generate a port level interrupt
0x1 Enable the propagation of Shadow register Write On Valid Error Interrupt to generate a port level interrupt
RW 0x0
19 Enable_SLVIF_WRONCHEN_ERR_IntSignal 
Slave Interface Write On Channel Enabled Error Signal Enable.
 - 0: Disable the propagation of Slave Interface Write On Channel enabled Error Interrupt to generate a port level interrupt
 - 1: Enable the propagation of Slave Interface Write On Channel enabled Error Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of Slave Interface Write On Channel enabled Error Interrupt to generate a port level interrupt
0x1 Enable the propagation of Slave Interface Write On Channel enabled Error Interrupt to generate a port level interrupt
RW 0x0
18 Enable_SLVIF_RD2RWO_ERR_IntSignal 
Slave Interface Read to write Only Error Signal Enable.
 - 0: Disable the propagation of Slave Interface Read to Write only Error Interrupt to generate a port level interrupt
 - 1: Enable the propagation of Slave Interface Read to Write Only Error Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of Slave Interface Read to Write only Error Interrupt to generate a port level interrupt
0x1 Enable the propagation of Slave Interface Read to Write Only Error Interrupt to generate a port level interrupt
RW 0x0
17 Enable_SLVIF_WR2RO_ERR_IntSignal 
Slave Interface Write to Read Only Error Signal Enable.
 - 0: Disable the propagation of Slave Interface Write to Read only Error Interrupt to generate a port level interrupt
 - 1: Enable the propagation of Slave Interface Write to Read Only Error Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of Slave Interface Write to Read only Error Interrupt to generate a port level interrupt
0x1 Enable the propagation of Slave Interface Write to Read Only Error Interrupt to generate a port level interrupt
RW 0x0
16 Enable_SLVIF_DEC_ERR_IntSignal 
Slave Interface Decode Error Signal Enable.
 - 0: Disable the propagation of Slave Interface Decode Error Interrupt to generate a port level interrupt
 - 1: Enable the propagation of Slave Interface Decode Error Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of Slave Interface Decode Error Interrupt to generate a port level interrupt
0x1 Enable the propagation of Slave Interface Decode Error Interrupt to generate a port level interrupt
RW 0x0
15 RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15 
DMAC Channelx Interrupt Status Enable Register (bit 15) Reserved bit - Read Only
 RO 0x0
14 Enable_SLVIF_MULTIBLKTYPE_ERR_IntSignal 
Slave Interface Multi Block type Error Signal Enable.
 - 0: Disable the propagation of Slave Interface Multi Block type Error Interrupt to generate a port level interrupt
 - 1: Enable the propagation of Slave Interface Multi Block type Error Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of Slave Interface Multi Block type Error Interrupt to generate a port level interrupt
0x1 Enable the propagation of Slave Interface Multi Block type Error Interrupt to generate a port level interrupt
RW 0x0
13 Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntSignal 
Shadow register or LLI Invalid Error Signal Enable.
 - 0: Disable the propagation of Shadow Register or LLI Invalid Error Interrupt to generate a port level interrupt
 - 1: Enable the propagation of Shadow Register or LLI Invalid  Error Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of Shadow Register or LLI Invalid Error Interrupt to generate a port level interrupt
0x1 Enable the propagation of Shadow Register or LLI Invalid Error Interrupt to generate a port level interrupt
RW 0x0
12 Enable_LLI_WR_SLV_ERR_IntSignal 
LLI WRITE Slave Error Signal Enable.
 - 0: Disable the propagation of LLI WRITE Slave Error Interrupt to generate a port level interrupt
 - 1: Enable the propagation of LLI WRITE Slave Error Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of LLI WRITE Slave Error Interrupt to generate a port level interrupt
0x1 Enable the propagation of LLI WRITE Slave Error Interrupt to generate a port level interrupt
RW 0x0
11 Enable_LLI_RD_SLV_ERR_IntSignal 
LLI Read Slave Error Signal Enable.
 - 0: Disable the propagation of LLI Read Slave Error Interrupt to generate a port level interrupt
 - 1: Enable the propagation of LLI Read Slave Error Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of LLI Read Slave Error Interrupt to generate a port level interrupt
0x1 Enable the propagation of LLI Read Slave Error Interrupt to generate a port level interrupt
RW 0x0
10 Enable_LLI_WR_DEC_ERR_IntSignal 
LLI WRITE Decode Error Signal Enable.
 - 0: Disable the propagation of LLI WRITE Decode Error Interrupt to generate a port level interrupt
 - 1: Enable the propagation of LLI WRITE Decode Error Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of LLI WRITE Decode Error Interrupt to generate a port level interrupt
0x1 Enable the propagation of LLI WRITE Decode Error Interrupt to generate a port level interrupt
RW 0x0
9 Enable_LLI_RD_DEC_ERR_IntSignal 
LLI Read Decode Error Signal Enable.
 - 0: Disable the propagation of LLI Read Decode Error Interrupt to generate a port level interrupt
 - 1: Enable the propagation of LLI Read Decode Error Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of LLI Read Decode Error Interrupt to generate a port level interrupt
0x1 Enable the propagation of LLI Read Decode Error Interrupt to generate a port level interrupt
RW 0x0
8 Enable_DST_SLV_ERR_IntSignal 
Destination Slave Error Signal Enable.
 - 0: Disable the propagation of Destination Slave Error Interrupt to generate a port level interrupt
 - 1: Enable the propagation of Destination Slave Error Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of Destination Slave Error Interrupt to generate a port level interrupt
0x1 Enable the propagation of Destination Slave Error Interrupt to generate a port level interrupt
RW 0x0
7 Enable_SRC_SLV_ERR_IntSignal 
Source Slave Error Signal Enable.
 - 0: Disable the propagation of Source Slave Error Interrupt to generate a port level interrupt
 - 1: Enable the propagation of Source Slave Error Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of Source Slave Error Interrupt to generate a port level interrupt
0x1 Enable the propagation of Source Slave Error Interrupt to generate a port level interrupt
RW 0x0
6 Enable_DST_DEC_ERR_IntSignal 
Destination Decode Error Signal Enable.
 - 0: Disable the propagation of Destination Decode Error Interrupt to generate a port level interrupt
 - 1: Enable the propagation of Destination Decode Error Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of Destination Decode Error Interrupt to generate a port level interrupt
0x1 Enable the propagation of Destination Decode Error Interrupt to generate a port level interrupt
RW 0x0
5 Enable_SRC_DEC_ERR_IntSignal 
Source Decode Error Signal Enable.
 - 0: Disable the propagation of Source Decode Error Interrupt to generate a port level interrupt
 - 1: Enable the propagation of Source Decode Error Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of Source Decode Error Interrupt to generate a port level interrupt
0x1 Enable the propagation of Source Decode Error Interrupt to generate a port level interrupt
RW 0x0
4 Enable_DST_TRANSCOMP_IntSignal 
Destination Transaction Completed Signal Enable.
 - 0: Disable the propagation of Destination Transaction complete Interrupt to generate a port level interrupt
 - 1: Enable the propagation of Destination Transaction complete Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of Destination Transaction complete Interrupt to generate a port level interrupt
0x1 Enable the propagation of Destination Transaction complete Interrupt to generate a port level interrupt
RW 0x0
3 Enable_SRC_TRANSCOMP_IntSignal 
Source Transaction Completed Signal Enable.
 - 0: Disable the propagation of Source Transaction Complete Interrupt to generate a port level interrupt
 - 1: Enable the propagation of Source Transaction Complete Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of Source Transaction Complete Interrupt to generate a port level interrupt
0x1 Enable the propagation of Source Transaction Complete Interrupt to generate a port level interrupt
RW 0x0
2 RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2 
DMAC Channelx Interrupt Status Enable Register (bit 2) Reserved bit - Read Only
 RO 0x0
1 Enable_DMA_TFR_DONE_IntSignal 
DMA Transfer Done Interrupt Signal Enable.
 - 0: Disable the propagation of DMA Transfer Done Interrupt to generate a port level interrupt
 - 1: Enable the propagation of DMA Transfer Done Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of DMA Transfer Done Interrupt to generate a port level interrupt
0x1 Enable the propagation of DMA Transfer Done Interrupt to generate a port level interrupt
RW 0x0
0 Enable_BLOCK_TFR_DONE_IntSignal 
Block Transfer Done Interrupt Signal Enable.
 - 0: Disable the propagation of Block Transfer Done Interrupt to generate a port level interrupt
 - 1: Enable the propagation of Block Transfer Done Interrupt to generate a port level interrupt
Value Description
0x0 Disable the propagation of Block Transfer Done Interrupt to generate a port level interrupt
0x1 Enable the propagation of Block Transfer Done Interrupt to generate a port level interrupt
RW 0x0