CQRS20

         CQRS20 - Response Mode Error Mask


Module Instance	Base Address	Register Address
`i_sdmmc__sdmmc_apb_slv__10808000____CQRS____SEG_L4_MP_sdmmc_s_0x0_0x1000`	`0x10808400`	`0x10808450`

Size: 32

Offset: 0x50

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`CQRMEM` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`CQRMEM` `RW 0x0`

CQRS20 Fields

Bit Name Description Access Reset

31:0

Bit	Name	Description	Access	Reset
31:0	`CQRMEM`	CQRMEM - Response Mode Error Mask\n CQE is able to automatically detect errors in response. The S/W defines which bits of the response need to be checked. All bits set to 1 (written by S/W) are analyzed. The CQE reports Response Error Detected Interrupt (CQREDI) when N bit of CQRMEM is 1 and N bit of response is 1. Response for SEND_QUEUE_STATUS (CMD13) automatically sent by CQE is ignored.	`RW`	`0x0`

CQRMEM

              CQRMEM - Response Mode Error Mask\n
              CQE is able to automatically detect errors in response.
              The S/W defines which bits of the response need to be checked. All bits set to 1 (written by S/W) are analyzed.
              The CQE reports Response Error Detected Interrupt (CQREDI) when N bit of CQRMEM is 1 and N bit of response is 1.
              Response for SEND_QUEUE_STATUS (CMD13) automatically sent by CQE is ignored.

RW

0x0